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| enhanced i/o flash type mcu with eeprom ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 revision: 1.60 date: october 24, 2011
table of contents technical document ...........................................................................8 features ...............................................................................................8 cpu features ........................................................................................................8 peripheral features ................................................................................................8 general description ............................................................................8 selection table ....................................................................................9 block diagram .....................................................................................9 pin assignment .................................................................................10 pin description ..................................................................................14 ht68f20 ..............................................................................................................14 ht68f30 ..............................................................................................................15 ht68f40 ..............................................................................................................16 ht68f50 ..............................................................................................................17 ht68f60 ..............................................................................................................18 absolute maximum ratings .............................................................20 d.c. characteristics ..........................................................................20 a.c. characteristics ..........................................................................22 comparator electrical characteristics ............................................23 power-on reset characteristics ......................................................24 system architecture .........................................................................25 clocking and pipelining ........................................................................................25 program counter ..................................................................................................26 stack ....................................................................................................................26 arithmetic and logic unit - alu ............................................................................26 flash program memory ....................................................................27 structure ...............................................................................................................27 special vectors .....................................................................................................27 look-up table .......................................................................................................27 table program example .......................................................................................27 in circuit programming .........................................................................................28 ram data memory.............................................................................29 structure ...............................................................................................................29 contents rev. 1.60 2 october 24, 2011 special function register description ...........................................32 indirect addressing registers - iar0, iar1....................................32 memory pointers - mp0, mp1 ...............................................................................32 bank pointer - b p.................................................................................................33 accumulator - acc ...............................................................................................34 program counter low register - pcl ..................................................................34 look-up table registers - tblp, tbhp, tblh ......................................................34 status register - status ....................................................................................34 eeprom data memory .....................................................................36 eeprom data memory structure ........................................................................36 eeprom registers ..............................................................................................36 reading data from the eeprom .........................................................................38 writing data to the eeprom ...............................................................................38 write protection ....................................................................................................39 eeprom interrupt ...............................................................................................39 programming considerations ...............................................................................39 oscillator............................................................................................40 oscillator overview ...............................................................................................40 system clock configurations ................................................................................40 external crystal/ ceramic oscillator - hxt ...........................................................41 external rc oscillator - erc ................................................................................41 internal rc oscillator - hirc ................................................................................41 external 32.768khz crystal oscillator - lxt .........................................................41 lxt oscillator low power function ......................................................................42 internal 32khz oscillator - lirc ...........................................................................42 supplementary oscillators ....................................................................................42 operating modes and system clocks .............................................43 system clocks ......................................................................................................43 system operation modes .....................................................................................44 control register ...................................................................................................45 fast wake-up .......................................................................................................46 operating mode switching and wake-up ..............................................................47 normal mode to slow mode switching ...........................................................47 slow mode to normal mode switching ...........................................................48 entering the sleep0 mode ..................................................................................48 entering the sleep1 mode ..................................................................................49 entering the idle0 mode .....................................................................................49 entering the idle1 mode .....................................................................................49 standby current considerations ...........................................................................49 wake-up ...............................................................................................................50 programming considerations ...............................................................................50 contents rev. 1.60 3 october 24, 2011 watchdog timer ................................................................................51 watchdog timer clock source .............................................................................51 watchdog timer control register .........................................................................51 watchdog timer operation ...................................................................................52 reset and initialisation .....................................................................53 reset functions ...................................................................................................53 reset initial conditions .........................................................................................54 input/output ports.............................................................................65 pull-high resistors ................................................................................................68 port a wake-up ....................................................................................................70 i/o port control registers .....................................................................................70 pin-remapping functions ......................................................................................73 pin-remapping registers ......................................................................................73 i/o pin structures .................................................................................................78 programming considerations ...............................................................................78 timer modules - tm...........................................................................79 introduction ..........................................................................................................79 tm operation .......................................................................................................80 tm clock source ..................................................................................................80 tm interrupts ........................................................................................................80 tm external pins ..................................................................................................80 tm input/output pin control registers .................................................................81 programming considerations ...............................................................................89 compact type tm - ctm...................................................................90 compact tm operation ........................................................................................90 compact type tm register description ...............................................................91 compact type tm operating modes ....................................................................94 compare match output mode ..............................................................................94 timer/counter mode .............................................................................................94 pwm output mode ...............................................................................................97 standard type tm - stm...................................................................99 standard tm operation ........................................................................................99 standard type tm register description ...............................................................99 standard type tm operating modes ..................................................................107 compare output mode .......................................................................................107 timer/counter mode ...........................................................................................110 pwm output mode .............................................................................................110 single pulse mode ..............................................................................................113 capture input mode ............................................................................................114 contents rev. 1.60 4 october 24, 2011 enhanced type tm - etm ...............................................................115 enhanced tm operation .....................................................................................115 enhanced type tm register description ............................................................116 enhanced type tm operating modes ................................................................121 compare output mode .......................................................................................121 timer/counter mode ...........................................................................................126 pwm output mode .............................................................................................126 single pulse output mode ..................................................................................131 capture input mode ............................................................................................133 comparators ....................................................................................135 comparator operation ........................................................................................135 comparator registers ........................................................................................135 comparator interrupt ..........................................................................................135 programming considerations .............................................................................135 serial interface module - sim .........................................................138 spi interface .......................................................................................................138 spi registers .....................................................................................................139 spi communication ............................................................................................142 i 2 c interface .......................................................................................................144 i 2 c bus communication ......................................................................................148 i 2 c bus start signal ............................................................................................148 slave address ....................................................................................................148 i 2 c bus read/write signal ..................................................................................148 i 2 c bus slave address acknowledge signal .......................................................148 i 2 c bus data and acknowledge signal ...............................................................149 peripheral clock output .................................................................151 peripheral clock operation .................................................................................151 interrupts..........................................................................................152 interrupt registers ..............................................................................................152 interrupt operation .............................................................................................164 external interrupt ................................................................................................168 comparator interrupt ..........................................................................................168 multi-function interrupt ........................................................................................168 time base interrupts ..........................................................................................168 serial interface module interrupt .........................................................................170 external peripheral interrupt ...............................................................................170 eeprom interrupt .............................................................................................170 lvd interrupt ......................................................................................................170 tm interrupts ......................................................................................................170 interrupt wake-up function ................................................................................171 programming considerations .............................................................................171 contents rev. 1.60 5 october 24, 2011 power down mode and wake-up ...................................................172 entering the idle or sleep mode .....................................................................172 standby current considerations .........................................................................172 wake-up .............................................................................................................172 low voltage detector - lvd............................................................173 lvd register ......................................................................................................173 lvd operation ....................................................................................................174 scom function for lcd .................................................................174 lcd operation ...................................................................................................174 lcd bias control ................................................................................................174 configuration options ....................................................................177 application circuits ........................................................................178 uart module serial interface ........................................................179 uart module features ......................................................................................179 uart module overview..................................................................179 uart module block diagram.........................................................179 pin assignment ...............................................................................180 uart module pin description .......................................................182 uart module d.c. characteristics................................................182 uart module a.c. characteristics................................................183 uart module functional description...........................................184 uart module internal signal .............................................................................184 uart module spi interface ............................................................184 spi timing ..........................................................................................................184 uart module external pin interfacing..........................................185 uart data transfer scheme .............................................................................185 uart commands ..............................................................................................186 uart status and control registers ...................................................................186 baud rate generator .........................................................................................191 uart module setup and control...................................................193 managing receiver errors ..................................................................................196 uart module interrupt structure ..................................................196 uart module power-down and wake-up .....................................197 using the uart function...............................................................198 application circuit with uart module..........................................199 contents rev. 1.60 6 october 24, 2011 instruction set .................................................................................200 introduction .........................................................................................................200 instruction timing ...............................................................................................200 moving and transferring data ............................................................................200 arithmetic operations .........................................................................................200 logical and rotate operations ...........................................................................200 branches and control transfer ...........................................................................200 bit operations .....................................................................................................201 table read operations .......................................................................................201 other operations ................................................................................................201 instruction set summary ....................................................................................201 instruction definition ......................................................................203 package information .......................................................................213 16-pin dip (300mil) outline dimensions .............................................................213 16-pin nsop (150mil) outline dimensions .........................................................216 16-pin ssop (150mil) outline dimensions .........................................................217 20-pin dip (300mil) outline dimensions .............................................................218 20-pin sop (300mil) outline dimensions ............................................................220 20-pin ssop (150mil) outline dimensions .........................................................221 24-pin skdip (300mil) outline dimensions ........................................................222 24-pin sop (300mil) outline dimensions ............................................................225 24-pin ssop (150mil) outline dimensions .........................................................226 28-pin skdip (300mil) outline dimensions ........................................................227 28-pin sop (300mil) outline dimensions ............................................................228 28-pin ssop (150mil) outline dimensions .........................................................229 saw type 32-pin (5mm 5mm) qfn outline dimensions ...................................230 saw type 40-pin (6mm 6mm for 0.75mm) qfn outline dimensions ................231 44-pin lqfp (10mm 10mm) (fp3.2mm) outline dimensions ............................232 48-pin ssop (300mil) outline dimensions .........................................................233 saw type 48-pin (7mm 7mm) qfn outline dimensions ...................................234 48-pin lqfp (7mm 7mm) outline dimensions ..................................................235 52-pin qfp (14mm 14mm) outline dimensions ................................................236 product tape and reel specifications ..........................................237 reel dimensions ................................................................................................237 carrier tape dimensions ....................................................................................239 contents rev. 1.60 7 october 24, 2011 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 enhanced i/o flash type mcu 8-bit mcu with eeprom rev. 1.60 8 october 24, 2011 general description the ht68fxx series of devices are flash memory i/o type 8-bit high performance risc architecture microcontrollers . offering users the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. multiple and extremely flexible timer modules provide timing, pulse generation and pwm generation func - tions. analog features include dual comparator func - tions. communication with the outside world is catered for by including fully integrated spi or i 2 c interface func - tions, two popular interfaces which provide designers with a means of easy communication with external pe - ripheral hardware. protective features such as an inter - nal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt, lxt, erc, hirc and lirc oscilla - tor functions are provided including a fully integrated system oscillator which requires no external compo - nents for its implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and mini - mise power consumption. the uart module is contained in the ht68fux0 series of devices. it can support the applications such as data com - munication networks between microcontrollers, low-cost data links between pcs and peripheral devices, portable and battery operated device communication, etc. the inclusion of flexible i/o programming features, time-base functions along with many other features en - sure that the devices will find excellent use in applica - tions such as electronic metering, environmental monitoring, handheld instruments, household appli - ances, electronically controlled tools, motor driving in addition to many others. features cpu features operating voltage: f sys = 8mhz: 2.2v~5.5v f sys = 12mhz: 2.7v~5.5v f sys = 20mhz: 4.5v~5.5v up to 0.2 s instruction cycle with 20mhz system clock at v dd =5v power down and wake-up functions to reduce power consumption five oscillators: external crystal -- hxt external 32.768khz crystal -- lxt external rc -- erc internal rc -- hirc internal 32khz rc -- lirc multi-mode operation: normal, slow, idle and sleep fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components all instructions executed in one or two instruction cycles table read instructions 63 powerful instructions up to 12-level subroutine nesting bit manipulation instruction peripheral features flash program memory: 1k 14 ~ 12k16 ram data memory: 64 8 ~ 5768 eeprom memory: 32 8~2568 watchdog timer function up to 50 bidirectional i/o lines software controlled 4-scom lines lcd driver with 1 / 2 bias multiple pin-shared external interrupts multiple timer module for time measure, input capture, compare match output, pwm output or single pulse output function serial interfaces module - sim for spi or i 2 c dual comparator functions dual time-base functions for generation of fixed time interrupt signals low voltage reset function low voltage detect function optional peripheral -- uart module for fully duplex asynchronous communication wide range of available package types flash program memory can be re-programmed up to 100,000 times flash program memory data retention > 10 years eeprom data memory can be re-programmed up to 1,000,000 times eeprom data memory data retention > 10 years technical document application note ha0075e mcu reset and oscillator circuits application note selection table most features are common to all devices, the main feature distinguishing them are memory capacity, i/o count, tm features, stack capacity and package types. the following table summarises the main features of each device. part no. vdd program memory data memory data eeprom i/o ext. int. timer module interface (spi/i 2 c) uart stack package ht68f20 2.2v~ 5.5v 1k 14 64 832 8182 10-bit ctm 1, 10-bit stm 1 4 16dip/nsop/ssop 20dip/sop/ssop ht68f30 2.2v~ 5.5v 2k 14 96 864 8 22 2 10-bit ctm 1, 10-bit etm 1 4 16dip/nsop/ssop 20dip/sop/ssop 24skdip/sop/ssop ht68fu30 14 24skdip/sop ht68f40 2.2v~ 5.5v 4k 15 192 8 1288 42 2 10-bit ctm 1, 10-bit etm 1, 16-bit stm 1 8 24/28skdip/sop/ssop 44lqfp 32/40qfn, 48ssop/qfn ht68fu40 34 40qfn, 44lqfp, 48ssop/qfn ht68f50 2.2v~ 5.5v 8k 16 384 8 2568 42 2 10-bit ctm 2, 10-bit etm 1, 16-bit stm 1 8 28skdip/sop/ssop 44lqfp, 40qfn 48ssop/qfn ht68fu50 34 44lqfp, 48qfn ht68f60 2.2v~ 5.5v 12k 16 576 8 2568 50 4 10-bit ctmx2, 10-bit etmx1, 16-bit stmx1 12 52qfp, 40qfn, 44lqfp 48ssop/lqfp/qfn ht68fu60 42 52qfp, 40qfn, 44lqfp 48lqfp/qfn note: as devices exist in more than one package format, the table reflects the situation for the package with the most pins. there is an additional peripheral known as the uart module in ht68fu30, ht68fu40, ht68fu50 and ht68fu60 devices. all information related to the uart module will be described in the following uart mod- ule section. block diagram ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 9 october 24, 2011 ! " # $ % & ' ( ( ' & ) * + * $ + , ( - . ( - . * / % 0 , 0 / pin assignment note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 10 october 24, 2011 + / / + + 1 2 , , 3 + 4 5 , , " + 6 5 / 2 / + 7 / ' * + 8 * * + + 9 2 ( 0 7 1 2 1 2 / 3 4 5 1 : , / " 6 ; 5 , < ; 5 < 1 : / 7 ; 5 / < , : / / 0 : 1 ; 2 < * , ; 2 1 < ; < * / ; 1 : , < ; * < ; 2 ( < / 8 / 7 / 6 / 4 / 1 / / / , = / 1 4 6 7 8 9 ! + / / : , + 1 2 , , 3 + 4 5 , , " + 6 5 / 2 / + 7 / ' * + 8 * * + + 9 2 ( 0 7 + , , ' , : , . 0 6 ' 1 0 4 ' / 0 1 1 0 / / . * * 0 , 1 , / = / ! / 9 / 8 / 7 / 6 / 4 / 1 / / / 1 4 6 7 8 9 ! = / , + / / : , + 1 2 , , 3 + 4 5 , , " + 6 5 / 2 / + 7 / ' * + 8 * * + + 9 2 ( 0 7 1 2 / 3 1 4 5 / " 4 + , , ' , : , . 0 6 ' 1 0 4 ' / 0 1 1 0 / / . * * 0 , / / , / : / , / 8 / 7 / 6 / 4 / 1 / / / , = / 1 4 6 7 8 9 ! + / / + + 1 2 , , 3 + 4 5 , , " + 6 5 / 2 / + 7 / ' * + 8 * * + + 9 2 ( 0 7 + , , ' , : , . 0 6 ' 1 0 4 ' / 0 1 1 0 / / . * * 0 , 1 , / = / ! / 9 / 8 / 7 / 6 / 4 / 1 / / / 1 4 6 7 8 9 ! = / , + / / + + 1 2 , , 3 + 4 5 , , " + 6 5 / 2 / + 7 / ' * + 8 * * + + 9 2 ( 0 7 1 2 / 3 4 5 / " + , , ' , : , . 0 6 ' 1 0 4 ' / 0 1 1 0 / / . * * 0 , / / 0 : / ; * < / , / 0 : , ; * * + < , 1 6 1 4 1 1 1 / 1 , / = / ! / 9 / 8 / 7 / 6 / 4 / 1 4 6 7 8 9 ! = / , / / / 1 + , , ' , : , . 0 6 ' 1 0 4 ' / 0 1 1 0 / / . * * 0 , / / 0 : / ; * < / , / 0 : , ; * * + < , 9 ; 2 ( < 4 8 ; < 1 + / / + + 1 2 , , 3 + 4 5 , , " + 6 5 / 2 / + 7 / ' * + 8 * * + + 9 2 ( 0 7 1 2 / 3 4 5 / " 6 ; 5 < 7 , : / ; 2 < 1 6 1 4 1 1 1 / 1 , / = / ! / 9 / 8 / 7 / 6 / 4 / 1 4 6 7 8 9 ! = / , / / / 1 + , , ' , : , . 0 6 ' 1 0 4 ' / 0 1 1 0 / / . * * 0 , / / 0 : / / , / 0 : , , 9 ; / + < 4 8 ; , : , < 1 + / / + + 1 2 , , 3 + 4 5 , , " + 6 5 / 2 / + 7 / ' * + 8 * * + + 9 2 ( 0 7 1 2 1 2 / 3 4 5 1 : , / " 6 ; 5 , < ; 5 < 1 : / 7 ; 5 / < , : / / 0 : 1 ; 2 < 1 ! 1 9 1 8 1 7 1 6 1 4 1 1 1 / 1 , / = / ! / 9 / 8 / 7 / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 + , , ' , : , . 0 6 ' 1 0 4 ' / 0 1 1 0 / / . * * 0 , / / 0 : / / , / 0 : , , 9 ; / + < 4 8 ; , : , < 1 * 4 ; 2 / < ; * < * 1 ; 2 , < ; * * + < note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 11 october 24, 2011 / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 1 71 81 91 !1 =4 ,4 /4 1 + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , / ; / ' < , ; , ' < 9 ; 5 / < * , ; 2 1 < ; < * / ; 1 : , < ; * < ; 2 ( < * 1 ; 2 , < ; * * + < * 4 ; 2 / < ; * < 8 ; , : , < 1 9 ; / + < 4 , / 0 : , , / / 0 : / / 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 7 ; 5 / < , : / / 0 : 1 ; 2 < 6 ; 5 , < ; 5 < 1 : / 4 5 1 : , / " 1 2 1 2 / 3 0 7 + 9 2 ( + 8 * * + + 7 / ' * / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 / 1 4 6 7 8 9 ! = / , / / / 1 4 8 4 7 4 6 4 4 4 1 4 / 4 , 1 = 1 ! 1 9 1 8 1 7 4 94 ! 4 = 6 ,6 / 6 1 6 46 6 6 7 6 86 9 6 ! 5 0 7 + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , 5 / ; / ' < * 1 ; 2 , < ; * * + < * / ; 1 : , < ; * < ; 2 ( < * , ; 2 1 < ; < 5 7 ; 5 / < , : / / 0 : 1 ; 2 < 6 ; 5 , < ; 5 < 1 : / 4 5 1 : , / " 1 2 1 2 / 3 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < * 4 ; 2 / < ; * < * 6 ; 1 : / < * 7 ; , : / < , / 1 4 8 ; , : , < 1 9 ; / + < 4 5 , / 0 : , , / / 0 : / / 6 ; / 0 : 1 < 7 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 9 ; 5 / < , ; , ' < / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 1 7 1 8 1 9 1 ! 1 = 4 , 4 / 4 1 4 4 4 64 74 84 94 !4 =6 ,6 /6 16 46 6 0 7 + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , / ; / ' < , ; , ' < * 4 ; 2 / < ; * < * 6 ; 1 : / < * 7 ; , : / < , / 1 4 8 ; , : , < 1 9 ; / + < 4 , / 0 : , , / / 0 : / / * 1 ; 2 , < ; * * + < * / ; 1 : , < ; * < ; 2 ( < * , ; 2 1 < ; < 7 ; 5 / < , : / / 0 : 1 ; 2 < 6 ; 5 , < ; 5 < 1 : / 4 5 1 : , / " 1 2 1 2 / 3 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < 6 ; / 0 : 1 < 7 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 9 ; 5 / < / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 1 7 1 8 1 9 1 ! 1 = 4 , 4 /4 14 44 64 74 84 94 !4 =6 , 0 7 + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , / ; / ' < 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 9 ; 5 / < , ; , ' < * / ; 1 : , < ; * < ; 2 ( < * , ; 2 1 < ; < 7 ; 5 / < , : / / 0 : 1 ; 2 < 6 ; 5 , < ; 5 < 1 : / 4 5 1 : , / " 1 2 1 2 / 3 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < * 1 ; 2 , < ; * * + < * 4 ; 2 / < ; * < * 6 ; 1 : / < * 7 ; , : / < 8 ; , : , < 1 9 ; / + < 4 , / 0 : , , / / 0 : / / 6 ; / 0 : 1 < 7 + / / + + 1 2 , , 3 + 4 5 , , " + 6 5 / 2 / + 7 / ' * + 8 * * + + 9 2 ( 0 7 0 8 ; * < 0 9 ; * * + < * 8 ; 2 ( < * 9 ; < 6 ; 5 , < ; 5 < 1 : / 5 5 5 1 2 1 2 / 3 4 5 1 : , / " 7 ; 5 / < , : / / 0 : 1 ; 2 < * , ; 2 1 < ; < * / ; 1 : , < ; * < ; 2 ( < * 1 ; 2 , < ; * * + < * 4 ; 2 / < ; * < * 6 ; 1 : / < 6 ! 6 9 6 8 6 7 6 6 6 4 6 1 6 / 6 , 4 = 4 ! 4 9 4 8 4 7 4 6 4 4 4 1 4 / 4 , 1 = 1 ! 1 9 1 8 1 7 / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 + , , ' , : , / ; / ' < , ; , ' < 9 ; 5 / < 8 ; 5 , < . 0 6 ' 1 0 4 ' / 0 1 1 0 / / . * * 0 , 7 6 ; / 0 : 1 < / / 0 : / / , / 0 : , , 5 9 ; / + < 4 8 ; , : , < 1 4 1 / , * 7 ; , : / < note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 12 october 24, 2011 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 / 1 4 6 7 8 9 ! = / , / / / 1 4 8 4 7 4 6 4 4 4 1 4 / 4 , 1 = 1 ! 1 9 1 8 1 7 4 9 4 !4 = 6 ,6 / 6 1 6 4 6 66 7 6 86 9 6 ! 5 0 7 + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , 5 / ; / ' < * 1 ; 2 , < ; * * + < * / ; 1 : , < ; * < ; 2 ( < * , ; 2 1 < 4 : / ; < 5 7 ; 5 / < , : / / 0 : 1 ; 2 < 6 ; 5 , < ; 5 < 2 4 1 : / 4 5 1 : , / " 1 2 1 2 / 3 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < * 4 ; 2 / < 4 : , ; * < * 6 ; 1 : / < * 7 ; , : / < , / 1 4 ; 4 : / < 8 ; , : , < 1 9 ; / + < 4 5 , / 0 : , , / / 0 : / / 6 ; / 0 : 1 < 7 ; 4 : , < 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 9 ; 5 / < , ; , ' < / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 1 7 1 8 1 9 1 ! 1 = 4 , 4 / 4 1 4 4 4 64 74 84 94 !4 =6 ,6 /6 16 46 6 0 7 + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , / ; / ' < , ; , ' < * 4 ; 2 / < 4 : , ; * < * 6 ; 1 : / < * 7 ; , : / < , / 1 4 ; 4 : / < 8 ; , : , < 1 9 ; / + < 4 , / 0 : , , / / 0 : / / 6 ; / 0 : 1 < 7 ; 4 : , < 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 9 ; 5 / < * 1 ; 2 , < ; * * + < * / ; 1 : , < ; * < ; 2 ( < * , ; 2 1 < 4 : / ; < 7 ; 5 / < , : / / 0 : 1 ; 2 < 6 ; 5 , < ; 5 < 2 4 1 : / 4 5 1 : , / " 1 2 1 2 / 3 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < 1 ! 1 9 1 8 1 7 1 6 1 4 1 1 1 / 1 , / = / ! / 9 / 8 / 7 / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 + , , ' , : , . 0 6 ' 1 0 4 ' / 0 1 1 0 / / . * * 0 , / / 0 : / / , / 0 : , , 9 ; / + < 4 8 ; , : , < 1 * 4 ; 2 / < 4 : , ; * < * 1 ; 2 , < ; * * + < + / / + + 1 2 , , 3 + 4 5 , , " + 6 5 / 2 / + 7 / ' * + 8 * * + + 9 2 ( 0 7 1 2 1 2 / 3 4 5 1 : , / " 6 ; 5 , < ; 5 < 2 4 1 : / 7 ; 5 / < , : / / 0 : 1 ; 2 < * , ; 2 1 < 4 : / ; < * / ; 1 : , < ; * < ; 2 ( < / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 1 7 1 8 1 9 1 ! 1 = 4 , 4 /4 14 44 64 74 84 94 !4 =6 , 0 7 + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , / ; / ' < 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 9 ; 5 / < , ; , ' < * / ; 1 : , < ; * < ; 2 ( < * , ; 2 1 < 4 : / ; < 7 ; 5 / < , : / / 0 : 1 ; 2 < 6 ; 5 , < ; 5 < 2 4 1 : / 4 5 1 : , / " 1 2 1 2 / 3 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < * 1 ; 2 , < ; * * + < * 4 ; 2 / < 4 : , ; * < * 6 ; 1 : / < * 7 ; , : / < 8 ; , : , < 1 9 ; / + < 4 , / 0 : , , / / 0 : / / 6 ; / 0 : 1 < 7 ; 4 : , < + / / + + 1 2 , , 3 + 4 5 , , " + 6 5 / 2 / + 7 / ' * + 8 * * + + 9 2 ( 0 7 0 8 ; * < 0 9 ; * * + < * 8 ; 2 ( < * 9 ; < 6 ; 5 , < ; 5 < 1 : / 5 5 5 1 2 1 2 / 3 4 5 1 : , / " 7 ; 5 / < , : / / 0 : 1 ; 2 < * , ; 2 1 < ; < * / ; 1 : , < ; * < ; 2 ( < * 1 ; 2 , < ; * * + < * 4 ; 2 / < ; * < * 6 ; 1 : / < 6 ! 6 9 6 8 6 7 6 6 6 4 6 1 6 / 6 , 4 = 4 ! 4 9 4 8 4 7 4 6 4 4 4 1 4 / 4 , 1 = 1 ! 1 9 1 8 1 7 / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 + , , ' , : , / ; / ' < , ; , ' < 9 ; 5 / < 8 ; 5 , < . 0 6 ' 1 0 4 ' / 0 1 1 0 / / . * * 0 , 7 ; 4 : , < 6 ; / 0 : 1 < / / 0 : / / , / 0 : , , 5 9 ; / + < 4 8 ; , : , < 1 4 ; 4 : / < 1 / , * 7 ; , : / < note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the / sign can be used for higher priority. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 13 october 24, 2011 / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 1 7 1 8 1 9 1 ! 1 = 4 , 4 /4 14 44 64 74 84 94 !4 =6 , 0 7 + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , / ; / ' < 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 9 ; 5 / < , ; , ' < * / ; 1 : , < ; * < ; 2 ( < * , ; 2 1 < 4 : / ; < 7 5 4 ; 5 / < , : / / 0 : 1 ; 2 < 6 5 1 ; 5 , < ; 5 < 2 4 1 : / 4 5 1 : , / " 1 2 1 2 / 3 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < * 1 ; 2 , < ; * * + < * 4 ; 2 / < 4 : , ; * < ; 2 ( < * 6 ; 1 : / < * 7 ; , : / < 8 ; , : , < 1 9 ; / + < 4 , / 0 : , , / / 0 : / / 6 ; / 0 : 1 < 7 ; 4 : , < * 1 ; 2 , < ; * * + < * / ; 1 : , < ; * < ; 2 ( < * , ; 2 1 < 4 : / ; < 7 5 4 ; 5 / < , : / / 0 : 1 ; 2 < 6 5 1 ; 5 , < ; 5 < 2 4 1 : / 4 5 1 : , / " 1 2 1 2 / 3 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 1 7 1 8 1 9 1 ! 1 = 4 , 4 / 4 1 4 4 4 64 74 84 94 !4 =6 ,6 /6 16 46 6 0 7 + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , / ; / ' < , ; , ' < * 4 ; 2 / < 4 : , ; * < ; 2 ( < * 6 ; 1 : / < * 7 ; , : / < , ; 5 , < / ; 5 / < 1 ; 5 1 < 4 ; 4 : / < 8 ; , : , < 1 9 ; / + < 4 , / 0 : , , / / 0 : / / 6 ; / 0 : 1 < 7 ; 4 : , < 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 9 ; 5 / < / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 / 1 4 6 7 8 9 ! = / , / / / 1 4 8 4 7 4 6 4 4 4 1 4 / 4 , 1 = 1 ! 1 9 1 8 1 7 4 9 4 ! 4 =6 , 6 / 6 16 4 6 6 6 76 8 6 9 6 ! 5 0 7 + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , 5 / ; / ' < * 1 ; 2 , < ; * * + < * / ; 1 : , < ; * < ; 2 ( < * , ; 2 1 < 4 : / ; < 5 7 5 4 ; 5 / < , : / / 0 : 1 ; 2 < 6 5 1 ; 5 , < ; 5 < 2 4 1 : / 4 5 1 : , / " 1 2 1 2 / 3 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < * 4 ; 2 / < 4 : , ; * < ; 2 ( < * 6 ; 1 : / < * 7 ; , : / < , ; 5 , < / ; 5 / < 1 ; 5 1 < 4 ; 4 : / < 8 ; , : , < 1 9 ; / + < 4 5 , / 0 : , , / / 0 : / / 6 ; / 0 : 1 < 7 ; 4 : , < 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 9 ; 5 / < , ; , ' < / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 4 6 4 7 4 8 4 9 4 ! 4 = 6 !6 =7 ,7 /7 1 1 4 1 6 1 7 1 8 1 9 1 ! 1 = 4 , 4 / 4 1 4 4 6 ,6 /6 16 46 6 6 76 86 9 4 1 0 7 + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , / ; / ' < , ; , ' < * 4 ; 2 / < 4 : , ; * < ; 2 ( < * 6 ; 1 : / < * 7 ; , : / < , ; 5 , < / ; 5 / < 1 ; 5 1 < 4 ; 4 : / < 8 9 > , ; , ' < > / ; / ' < 8 ; , : , < 1 9 ; / + < 4 * 1 ; 2 , < ; * * + < * / ; 1 : , < ; * < ; 2 ( < * , ; 2 1 < 4 : / ; < 7 5 4 ; 5 / < , : / / 0 : 1 ; 2 < 6 5 1 ; 5 , < ; 5 < 2 4 1 : / 4 5 1 : , / " 1 2 1 2 / 3 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < 7 6 , / 0 : , , / / 0 : / / 6 ; / 0 : 1 < 7 ; 4 : , < 0 , . * * 0 / / 0 1 1 0 4 ' / 0 6 ' 1 . 8 ; 5 , < 9 ; 5 / < 1 2 1 2 / 3 4 5 1 : , / " 6 5 1 ; 5 , < ; 5 < 2 4 1 : / 7 5 4 ; 5 / < , : / / 0 : 1 ; 2 < * , ; 2 1 < 4 : / ; < * / ; 1 : , < ; * < ; 2 ( < * 1 ; 2 , < ; * * + < * 4 ; 2 / < 4 : , ; * < ; 2 ( < * 6 ; 1 : / < * 7 ; , : / < , ; 5 , < / ; 5 / < 1 ; 5 1 < 4 ; 4 : / < > / ; / ' < 8 ; , : , < 1 9 ; / + < 4 , / 0 : , , / / 0 : / / 6 ; / 0 : 1 < 7 ; 4 : , < 0 , . * * 0 / / 6 ! 6 9 6 8 6 7 6 6 6 4 6 1 6 / 6 , 4 = 4 ! 4 9 4 8 4 7 4 6 4 4 4 1 4 / 4 , 1 = 1 ! 1 9 1 8 1 7 / 1 4 6 7 8 9 ! = / , / / / 1 / 4 / 6 / 7 / 8 / 9 / ! / = 1 , 1 / 1 1 1 4 1 6 5 5 * 9 ; < * 8 ; 2 ( < 0 9 ; * * + < 0 8 ; * < 1 0 7 . + 9 2 ( + 8 * * + + 7 / ' * + 6 5 / 2 / + 4 5 , , " + 1 2 , , 3 + / / + + , , ' , : , / ; / ' < , ; , ' < 9 ; 5 / < 8 ; 5 , < . 0 6 ' 1 0 4 ' / 0 1 1 pin description with the exception of the power pins, all pins on these devices can be referenced by their port name, e.g. pa.0, pa.1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the serial port pins etc. the function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. the following tables only include the pins which are directly related to the mcu. the pin descriptions of the additional peripheral functions are located at the end of the datasheet along with the relevant peripheral function functional de - scription. ht68f20 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb5 port b pbpu st cmos pc0~pc3 port c pcpu st cmos c0-, c1- comparator 0, 1 input cp0c cp1c an pa3, pc3 c0+, c1+ comparator 0, 1 input an pa2, pc2 c0x, c1x comparator 0, 1 output cmos pa0, pa5 tck0, tck1 tm0, tm1 input st pa2, pa4 tp0_0 tm0 i/o tmpc0 st cmos pa0 tp1_0, tp1_1 tm1 i/o tmpc0 st cmos pa1, pc0 int0, int1 ext. interrupt 0, 1 st pa3, pa4 pint peripheral interrupt st pc3 pck peripheral clock output cmos pc2 sdi spi data input st pa6 sdo spi data output cmos pa5 scs spi slave select st cmos pb5 sck spi serial clock st cmos pa7 scl i 2 c clock st nmos pa7 sda i 2 c data st nmos pa6 scom0~scom3 scom0~scom3 scomc scom pc0, pc1, pc2, pc3 osc1 hxt/erc pin co hxt pb1 osc2 hxt pin co hxt pb2 xt1 lxt pin co lxt pb3 xt2 lxt pin co lxt pb4 res reset input co st pb0 vdd power supply pwr vss ground pwr note: i/t: input type; o/t: output type op: optional by configuration option (co) or register option pwr: power; co: configuration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 14 october 24, 2011 ht68f30 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb5 port b pbpu st cmos pc0~pc7 port c pcpu st cmos c0-, c1- comparator 0, 1 input cp0c cp1c an pa3, pc3 c0+, c1+ comparator 0, 1 input an pa2, pc2 c0x, c1x comparator 0, 1 output cmos pa0, pa5 tck0, tck1 tm0, tm1 input st pa2, pa4 tp0_0, tp0_1 tm0 i/o tmpc0 st cmos pa0, pc5 tp1a tm1 i/o tmpc0 st cmos pa1 tp1b_0, tp1b_1 tm1 i/o tmpc0 st cmos pc0, pc1 int0, int1 ext. interrupt 0, 1 st pa3, pa4 pint peripheral interrupt prm0 st pc3 or pc4 pck peripheral clock output prm0 cmos pc2 or pc5 sdi spi data input prm0 st pa6 or pc0 sdo spi data output prm0 cmos pa5 or pc1 scs spi slave select prm0 st cmos pb5 or pc6 sck spi serial clock prm0 st cmos pa7 or pc7 scl i 2 c clock prm0 st nmos pa7 or pc7 sda i 2 c data prm0 st nmos pa6 or pc0 scom0~scom3 scom0~scom3 scomc scom pc0, pc1, pc6, pc7 osc1 hxt/erc pin co hxt pb1 osc2 hxt pin co hxt pb2 xt1 lxt pin co lxt pb3 xt2 lxt pin co lxt pb4 res reset input co st pb0 vdd power supply pwr vss ground pwr note: i/t: input type; o/t: output type op: optional by configuration option (co) or register option pwr: power; co: configuration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 15 october 24, 2011 ht68f40 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb7 port b pbpu st cmos pc0~pc7 port c pcpu st cmos pd0~pd7 port d pdpu st cmos pe0~pe7 port e pepu st cmos pf0~pf1 port f pfpu st cmos c0-, c1- comparator 0, 1 input cp0c cp1c an pa3, pc3 c0+, c1+ comparator 0, 1 input cp0c cp1c an pa2, pc2 c0x, c1x comparator 0, 1 output cp0c cp1c prm0 cmos pa0, pa5 or pf0, pf1 tck0~tck2 tm0~tm2 input prm1 st pa2, pa4, pc2 or pd2, pd3, pd0 tp0_0, tp0_1 tm0 i/o tmpc0 prm2 st cmos pa0, pc5 or pc6, pd5 tp1a tm1 i/o tmpc0 prm2 st cmos pa1 or pc7 tp1b_0~tp1b_2 tm1 i/o tmpc0 prm2 st cmos pc0, pc1, pc5 or , , pe4 tp2_0, tp2_1 tm2 i/o tmpc1 prm2 st cmos pc3, pc4 or pd1, pd4 int0, int1 ext. interrupt 0, 1 prm1 st pa3, pa4 or pc4, pc5 or pe6, pe7 pint peripheral interrupt prm0 st pc3 or pc4 pck peripheral clock output prm0 cmos pc2 or pc5 sdi spi data input prm0 st pa6 or pd2 or pb7 sdo spi data output prm0 cmos pa5 or pd3 or pb6 scs spi slave select prm0 st cmos pb5 or pd0 or pd7 sck spi serial clock prm0 st cmos pa7 or pd1 or pd6 scl i 2 c clock prm0 st nmos pa7 or pd1 or pd6 sda i 2 c data prm0 st nmos pa6 or pd2 or pb7 scom0~scom3 scom0~scom3 scomc scom pc0, pc1, pc6, pc7 osc1 hxt/erc pin co hxt pb1 osc2 hxt pin co hxt pb2 xt1 lxt pin co lxt pb3 xt2 lxt pin co lxt pb4 res reset input co st pb0 vdd power supply pwr vss ground pwr ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 16 october 24, 2011 note: i/t: input type; o/t: output type op: optional by configuration option (co) or register option pwr: power; co: configuration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ht68f50 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb7 port b pbpu st cmos pc0~pc7 port c pcpu st cmos pd0~pd7 port d pdpu st cmos pe0~pe7 port e pepu st cmos pf0~pf1 port f pfpu st cmos c0-, c1- comparator 0, 1 input cp0c cp1c an pa3, pc3 c0+, c1+ comparator 0, 1 input cp0c cp1c an pa2, pc2 c0x, c1x comparator 0, 1 output cp0c cp1c prm0 cmos pa0, pa5 or pf0, pf1 tck0~tck3 tm0~tm3 input prm1 st pa2, pa4, pc2, pc4 or pd2, pd3, pd0, tp0_0, tp0_1 tm0 i/o tmpc0 prm2 st cmos pa0, pc5 or pc6, pd5 tp1a tm1 i/o tmpc0 prm2 st cmos pa1 or pc7 tp1b_0~tp1b_2 tm1 i/o tmpc0 prm2 st cmos pc0, pc1, pc5 or , , pe4 tp2_0, tp2_1 tm2 i/o tmpc1 prm2 st cmos pc3, pc4 or pd1, pd4 tp3_0, tp3_1 tm3 i/o tmpc1 prm2 st cmos pd3, pd0 or pe5, pe3 int0, int1 ext. interrupt 0, 1 prm1 st pa3, pa4 or pc4, pc5 or pe6, pe7 pint peripheral interrupt prm0 st pc3 or pc4 pck peripheral clock output prm0 cmos pc2 or pc5 sdi spi data input prm0 st pa6 or pd2 or pb7 sdo spi data output prm0 cmos pa5 or pd3 or pb6 scs spi slave select prm0 st cmos pb5 or pd0 or pd7 sck spi serial clock prm0 st cmos pa7 or pd1 or pd6 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 17 october 24, 2011 pin name function op i/t o/t pin-shared mapping scl i 2 c clock prm0 st nmos pa7 or pd1 or pd6 sda i 2 c data prm0 st nmos pa6 or pd2 or pb7 scom0~scom3 scom0~scom3 scomc scom pc0, pc1, pc6, pc7 osc1 hxt/erc pin co hxt pb1 osc2 hxt pin co hxt pb2 xt1 lxt pin co lxt pb3 xt2 lxt pin co lxt pb4 res reset input co st pb0 vdd power supply pwr vss ground pwr note: i/t: input type; o/t: output type op: optional by configuration option (co) or register option pwr: power; co: configuration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ht68f60 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb7 port b pbpu st cmos pc0~pc7 port c pcpu st cmos pd0~pd7 port d pdpu st cmos pe0~pe7 port e pepu st cmos pf0~pf7 port f pfpu st cmos pg0~pg1 port g pgpu st cmos c0-, c1- comparator 0, 1 input cp0c cp1c an pa3, pc3 c0+, c1+ comparator 0, 1 input cp0c cp1c an pa2, pc2 c0x, c1x comparator 0, 1 output cp0c cp1c prm0 cmos pa0, pa5 or pf0, pf1 or pg0, pg1 tck0~tck3 tm0~tm3 input prm1 st pa2, pa4, pc2, pc4 or pd2, pd3, pd0, tp0_0, tp0_1 tm0 i/o tmpc0 prm2 st cmos pa0, pc5 or pc6, pd5 tp1a tm1 i/o tmpc0 prm2 st cmos pa1 or pc7 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 18 october 24, 2011 pin name function op i/t o/t pin-shared mapping tp1b_0~tp1b_2 tm1 i/o tmpc0 prm2 st cmos pc0, pc1, pc5 or , , pe4 tp2_0, tp2_1 tm2 i/o tmpc1 prm2 st cmos pc3, pc4 or pd1, pd4 tp3_0, tp3_1 tm3 i/o tmpc1 prm2 st cmos pd3, pd0 or pe5, pe3 int0~int3 ext. interrupt 0~3 prm1 st pa3, pa4, pc4, pc5 or pc4, pc5, pe2, ,or pe0, pe1, , or pe6, pe7, , pint peripheral interrupt prm0 st pc3 or pc4 pck peripheral clock output prm0 cmos pc2 or pc5 sdi spi data input prm0 st pa6 or pd2 or pb7 sdo spi data output prm0 cmos pa5 or pd3 or pb6 or pd1 scs spi slave select prm0 st cmos pb5 or pd0 or pd7 sck spi serial clock prm0 st cmos pa7 or pd1 or pd6 or pd3 scl i 2 c clock prm0 st nmos pa7 or pd1 or pd6 or pd3 sda i 2 c data prm0 st nmos pa6 or pd2 or pb7 scom0~scom3 scom0~scom3 scomc scom pc0, pc1, pc6, pc7 osc1 hxt/erc pin co hxt pb1 osc2 hxt pin co hxt pb2 xt1 lxt pin co lxt pb3 xt2 lxt pin co lxt pb4 res reset input co st pb0 vdd power supply pwr vss ground pwr note: i/t: input type; o/t: output type op: optional by configuration option (co) or register option pwr: power; co: configuration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 19 october 24, 2011 absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ................................................................80ma i oh total.............................................................. 80ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage (hxt, erc, hirc) f sys =8mhz 2.2 5.5 v f sys =12mhz 2.7 5.5 v f sys =20mhz 4.5 5.5 v i dd1 operating current, normal mode, f sys =f h (hxt, erc, hirc) 3v no load, f sys =f h =4mhz, wdt enable 0.7 1.1 ma 5v 1.8 2.7 ma 3v no load, f sys =f h =8mhz, wdt enable 1.6 2.4 ma 5v 3.3 5.0 ma 3v no load, f sys =f h =12mhz, wdt enable 2.2 3.3 ma 5v 5.0 7.5 ma i dd2 operating current, normal mode, f sys =f h (hxt) 5v no load, f sys =f h =20mhz, wdt enable 6.0 9.0 ma i dd3 operating current, slow mode, f sys =f l (lxt, lirc) 3v no load, f sys =f l , wdt enable 10 20 a 5v 30 50 a i idle0 idle0 mode standby current (lxt or lirc on) 3v no load, wdt enable 1.5 3.0 a 5v 3.0 6.0 a i idle1 idle1 mode standby current (hxt, erc, hirc) 3v no load, wdt enable, f sys =12mhz on 0.55 0.83 ma 5v 1.30 2.00 ma i sleep0 sleep0 mode standby current (lxt and lirc off) 3v no load, wdt disable 1 a 5v 2 a i sleep1 sleep1 mode standby current (lxt or lirc on) 3v no load, wdt enable 1.5 3.0 a 5v 2.5 5.0 a v il1 input low voltage for i/o ports or input pins except res pin 0 0.3v dd v v ih1 input high voltage for i/o ports or input pins except res pin 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 20 october 24, 2011 symbol parameter test conditions min. typ. max. unit v dd conditions v lvr lvr voltage level lvr enable, 2.10v option 5% 2.10 +5% v lvr enable, 2.55v option 5% 2.55 +5% v lvr enable, 3.15v option 5% 3.15 +5% v lvr enable, 4.20v option 5% 4.20 +5% v v lvd lvd voltage level lvden=1, v lvd =2.0v 5% 2.00 +5% v lvden=1, v lvd =2.2v 5% 2.20 +5% v lvden=1, v lvd =2.4v 5% 2.40 +5% v lvden=1, v lvd =2.7v 5% 2.70 +5% v lvden=1, v lvd =3.0v 5% 3.00 +5% v lvden=1, v lvd =3.3v 5% 3.30 +5% v lvden=1, v lvd =3.6v 5% 3.60 +5% v lvden=1, v lvd =4.4v 5% 4.40 +5% v i lv additional power consumption if lvr and lvd is used lvr enable, lvden=0 60 90 a lvr disable, lvden=1 75 115 a lvr enable, lvden=1 90 135 a v ol output low voltage i/o port 3v i ol =9ma 0.3 v 5v i ol =20ma 0.5 v v oh output high voltage i/o port 3v i oh =3.2ma 2.7 v 5v i oh =7.4ma 4.5 v r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k i scom scom operating current 5v scomc, isel[1:0]=00 17.5 25.0 32.5 a scomc, isel[1:0]=01 35 50 65 a scomc, isel[1:0]=10 70 100 130 a scomc, isel[1:0]=11 140 200 260 a v scom v dd /2 voltage for lcd com 5v no load 0.475 0.500 0.525 v dd ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 21 october 24, 2011 ta=25 c a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu operating clock 2.2v~5.5v dc 8 mhz 2.7v~5.5v dc 12 mhz 4.5v~5.5v dc 20 mhz f sys system clock (hxt) 2.2v~5.5v 0.4 8 mhz 2.7v~5.5v 0.4 12 mhz 4.5v~5.5v 0.4 20 mhz f hirc system clock (hirc) 3v/5v ta=25 c 2% 4 +2% mhz 3v/5v ta=25 c 2% 8 +2% mhz 5v ta=25 c 2% 12 +2% mhz 3v/5v ta=0~70 c 5% 4 +5% mhz 3v/5v ta=0~70 c 4% 8 +4% mhz 5v ta=0~70 c 5% 12 +3% mhz 2.2v~ 3.6v ta=0~70 c 7% 4 +7% mhz 3.0v~ 5.5v ta=0~70 c 5% 4 +9% mhz 2.2v~ 3.6v ta=0~70 c 6% 8 +4% mhz 3.0v~ 5.5v ta=0~70 c 4% 8 +9% mhz 3.0v~ 5.5v ta=0~70 c 6% 12 +7% mhz 2.2v~ 3.6v ta= 40 c~85 c 12% 4 +8% mhz 3.0v~ 5.5v ta= 40 c~85 c 10% 4 +9% mhz 2.2v~ 3.6v ta= 40 c~85 c 15% 8 +4% mhz 3.0v~ 5.5v ta= 40 c~85 c 8% 8 +9% mhz 3.0v~ 5.5v ta= 40 c~85 c 12% 12 +7% mhz f erc system clock (erc) 5v ta=25 c, r=120k * 2% 8 +2% mhz 5v ta=0~70 c, r=120k * 5% 8 +6% mhz 5v ta= 40 c~85 c, r=120k * 7% 8 +9% mhz 3.0v~ 5.5v ta= 40 c~85 c, r=120k * 9% 8 +10% mhz 2.2v~ 5.5v ta= 40 c~85 c, r=120k * 15% 8 +10% mhz f lxt system clock (lxt) 32.768 khz ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 22 october 24, 2011 symbol parameter test conditions min. typ. max. unit v dd conditions f lirc system clock (lirc) 5v ta=25 c 10% 32 +10% khz 2.2v~ 5.5v ta=40 c~+85 c 50% 32 +60% khz f timer timer input pin frequency 1 f sys t res external reset low pulse width 1 s t int interrupt pulse width 1 t sys t lvr low voltage width to reset 120 240 480 s t lvd low voltage width to interrupt 20 45 90 s t lvds lvdo stable time 15 s t bgs vbg turn on stable time 200 s t eerd eeprom read time 45 90 s t eewr eeprom write time 24ms t sst system start-up timer period (wake-up from halt) f sys =hxt or lxt 1024 t sys f sys =erc or hirc 15~16 f sys =lirc osc 1~2 note: 1. t sys =1/f sys 2. * for f erc , as the resistor tolerance will influence the frequency a precision resistor is recommended. 3. to maintain the accuracy of the internal hirc oscillator frequency, a 0.1 f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. comparator electrical characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v cmp comparator operating voltage 2.2 5.5 v i cmp comparator operating current 3v 37 56 a 5v 130 200 a v cmpos comparator input offset voltage 10 10 mv v hys hysteresis width 20 40 60 mv v cm comparator common mode voltage range v ss v dd 1.4v v a ol comparator open loop gain 60 80 db t pd comparator response time with 100mv overdrive (note) 370 560 ns note: measured with comparator one input pin at v cm =(v dd 1.4)/2 while the other pin input transition from vss to (v cm +100mv) or from v dd to (v cm -100mv). ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 23 october 24, 2011 ta=25 c power-on reset characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv rr vdd vdd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 1 ms ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 24 october 24, 2011 . * * . . * * ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 25 october 24, 2011 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their in - ternal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, in - crement, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accu - mulator and the alu. certain internal registers are im - plemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and flexibility. this makes the de - vice suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, lxt, hirc, lirc or erc oscillator is subdivided into four in- ternally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. ? @ ? " / ? 3 / @ ? ? 3 1 @ ? 3 / 3 / 3 1 a b ) ) / ) 1 ) 4 ) 6 % system clocking and pipelining ? / @ ? / ? 1 % / 1 4 6 7 8 * ( + b c . + d ; / 1 & < + ( ( * ( + b ( ; / 1 & < c c 5 @ ? 1 ? 4 ? 8 @ ? 8 ? 9 instruction fetching ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 26 october 24, 2011 program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low regis - ter, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. device program counter program counter high byte pcl register ht68f20 pc9, pc8 pcl7~pcl0 ht68f30 pc10~pc8 ht68f40 pc11~pc8 ht68f50 pc12~pc8 ht68f60 pc13~pc8 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short pro- gram jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 loca - tions. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manip - ulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. the acti - vated level is indexed by the stack pointer, and is nei - ther readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the pro - gram counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is re - stored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overflow, the first program counter save in the stack will be lost. device stack levels ht68f20/ht68f30 4 ht68f40/ht68f50 8 ht68f60 12 arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic oper- ations of the instruction set. connected to the main microcontroller data bus, the alu receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper - ations may result in carry, borrow or other status changes, the status register will be correspondingly up - dated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti ) ( e / ) ( e 1 ) ( e 4 ) ( e 5 % a ) ) 0 a ) ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 27 october 24, 2011 flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifi - cation on the same device. by using the appropriate programming tools, these flash devices offer users the flexibility to conveniently debug and develop their appli - cations while also offering a means of field programming and updating. structure the program memory has a capacity of 1k 14 bits to 12k 16 bits. the program memory is addressed by the program counter and also contains data, table informa - tion and interrupt entries. table data, which can be setup in any location within the program memory, is ad - dressed by a separate table pointer register. device capacity banks ht68f20 1k14 0 ht68f30 2k14 0 ht68f40 4k15 0 ht68f50 8k16 0 ht68f60 12k16 0, 1 the ht68f60 has its program memory divided into two banks, bank 0 and bank 1. the required bank is se- lected using bit 5 of the bp register. special vectors within the program memory, certain locations are re- served for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialis - ation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers define the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the tabrd[m] or tabrdl[m] instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data flow of the look-up table. table program example the following example shows how the table pointer and table data is defined and retrieved from the microcontroller. this example uses raw table data lo - cated in the program memory which is stored there us - % . , , , 6 & , 4 & / 6 # , , 1 & % . / 6 # , 9 & % . / 7 # % . / 8 # % . , , , , & , , 4 & 0 ) , / 8 # , & / & / & 1 , , , & 1 & 0 ) / program memory structure 0 ( & $ & 0 ( - 0 0 ( * + / 6 f / 8 # ! ( % 0 & ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 28 october 24, 2011 ing the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k program memory of the ht68f30. the table pointer is setup here to have an ini - tial value of 06h . this will ensure that the first data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is refer - enced to the first address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter - rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit us - ing a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards com - plete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufac - turers to easily keep their manufactured products sup - plied with the latest program releases without removal and re-insertion of the device. mcu programming pins function pa0 serial data input/output pa2 serial clock res device reset vdd power supply vss ground the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two ad - ditional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supple- mentary literature. during the programming process the res pin will be held low by the programmer disabling the normal opera- tion of the microcontroller and taking control of the pa0 and pa2 i/o pins for data and clock programming pur- poses. the user must there take care to ensure that no other outputs are connected to these two pins. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address mov tblp,a ; is referenced mov a,07h ; initialise high table pointer tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 705h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 29 october 24, 2011 programmer pin mcu pins res pb0 data pa0 clk pa2 programmer and mcu pins ram data memory the data memory is a volatile area of 8-bit wide ram in- ternal memory and is the location where temporary in- formation is stored. structure divided into two sections, the first of these is an area of ram, known as the special function data memory. here are located registers which are necessary for cor - rect operation of the device. many of these registers can be read from and written to directly under program con - trol, however, some remain protected from user manipu - lation. device capacity banks ht68f20 648 0: 60h~7fh 1: 60h~7fh ht68f30 968 0: 60h~7fh 1: 60h~7fh 2: 60h~7fh ht68f40 1928 0: 80h~ffh 1: 80h~bfh ht68f50 3848 0: 80h~ffh 1: 80h~ffh 2: 80h~ffh ht68f60 5768 0: 80h~ffh 1: 80h~ffh 2: 80h~ffh 3: 80h~ffh 4: 80h~bfh g g g : . * * * + + ( 2 : . * + + ( 2 . . * * $ note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. , , & , / & , 1 & , 4 & , 6 & , 7 & , 8 & , 9 & , ! & , = & , + & , 0 & , & , * & , & , & / , & / / & / 1 & / 4 & / 6 & / 7 & / 8 & / 9 & / ! & / = & / + & / 0 & / & / * & / & / & 1 , & 1 / & 1 1 & 1 4 & 1 6 & 1 7 & 1 8 & 1 9 & 1 ! & 1 = & 1 + & 1 0 & 1 & 1 * & 1 & 1 & + , , + / / 0 + ( 0 ( 0 ( & 0 & + $ * ( . * 5 > * 0 5 , 5 / 5 1 $ , / 1 $ + $ + $ + + 0 $ 0 0 $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 4 , & 4 / & 4 1 & 4 4 & 4 6 & 4 7 & 4 8 & 4 9 & 4 ! & 4 = & 4 + & 4 0 & 4 & 4 * & 4 & 4 & 6 , & 6 / & 6 1 & 6 4 & 6 6 & 6 7 & 6 8 & 6 9 & 6 ! & 6 = & 6 + & 6 0 & 6 & 6 * & 6 & 6 & 7 , & 7 / & 7 1 & 7 4 & 7 6 & 7 7 & 7 8 & 7 9 & 7 ! & 7 = & 7 + & 7 0 & 7 & 7 * & 7 & 7 & $ $ $ $ , / , / * + 1 , , , / , * ( , * & , + ( , + & $ + * , $ $ $ $ / , / / $ / * ( / * & / + ( / + & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ " # $ % " # $ " # $ ht68f20 special purpose data memory ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 30 october 24, 2011 , , & , / & , 1 & , 4 & , 6 & , 7 & , 8 & , 9 & , ! & , = & , + & , 0 & , & , * & , & , & / , & / / & / 1 & / 4 & / 6 & / 7 & / 8 & / 9 & / ! & / = & / + & / 0 & / & / * & / & / & 1 , & 1 / & 1 1 & 1 4 & 1 6 & 1 7 & 1 8 & 1 9 & 1 ! & 1 = & 1 + & 1 0 & 1 & 1 * & 1 & 1 & + , , + / / 0 + ( 0 ( 0 ( & 0 & + $ * ( . * 5 > * 0 5 , 5 / 5 1 $ , / 1 $ + $ + $ + + 0 $ 0 0 $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 4 , & 4 / & 4 1 & 4 4 & 4 6 & 4 7 & 4 8 & 4 9 & 4 ! & 4 = & 4 + & 4 0 & 4 & 4 * & 4 & 4 & 6 , & 6 / & 6 1 & 6 4 & 6 6 & 6 7 & 6 8 & 6 9 & 6 ! & 6 = & 6 + & 6 0 & 6 & 6 * & 6 & 6 & 7 , & 7 / & 7 1 & 7 4 & 7 6 & 7 7 & 7 8 & 7 9 & 7 ! & 7 = & 7 + & 7 0 & 7 & 7 * & 7 & 7 & $ $ $ $ , / , / * + 1 , , , / , * ( , * & , + ( , + & $ + * , $ , $ $ / , / / / 1 / * ( / * & / + ( / + & / 0 ( / 0 & $ $ $ $ $ $ $ $ $ $ $ $ $ $ " # $ % % " # $ % " # $ ht68f30 special purpose data memory , , & , / & , 1 & , 4 & , 6 & , 7 & , 8 & , 9 & , ! & , = & , + & , 0 & , & , * & , & , & / , & / / & / 1 & / 4 & / 6 & / 7 & / 8 & / 9 & / ! & / = & / + & / 0 & / & / * & / & / & 1 , & 1 / & 1 1 & 1 4 & 1 6 & 1 7 & 1 8 & 1 9 & 1 ! & 1 = & 1 + & 1 0 & 1 & 1 * & 1 & 1 & 4 , & 4 / & 4 1 & 4 4 & 4 6 & 4 7 & 4 8 & 4 9 & 4 ! & 4 = & 4 + & 4 0 & 4 & 4 * & 4 & 4 & 6 , & 6 / & 6 1 & 6 4 & 6 6 & 6 7 & 6 8 & 6 9 & 6 ! & 6 = & 6 + & 6 0 & 6 & 6 * & 6 & 6 & 7 , & 7 / & 7 1 & 7 4 & 7 6 & 7 7 & 7 8 & 7 9 & 7 ! & 7 = & 7 + & 7 0 & 7 & 7 * & 7 & 7 & 8 , & 8 / & 8 1 & 8 4 & 8 6 & 8 7 & 8 8 & 8 9 & 8 ! & 8 = & 8 + & 8 0 & 8 & 8 * & 8 & 8 & 9 , & 9 / & 9 1 & 9 4 & 9 6 & 9 7 & 9 8 & 9 9 & 9 ! & 9 = & 9 + & 9 0 & 9 & 9 * & 9 & 9 & " # $ % " # $ " # $ $ + * , / , / 1 / , / / / 1 / * ( / * & / + ( / + & / 0 ( / 0 & 1 , 1 / 1 * ( 1 * & 1 + ( 1 + & 1 $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ + , , + / / 0 + ( 0 ( 0 ( & 0 & + $ * ( . * 5 > * 0 5 , 5 / 5 1 $ , / 1 $ + $ + $ + + 0 $ 0 0 $ * $ * * $ $ $ $ $ $ $ $ $ $ $ , / , / * + 1 , , , / , * ( , * & , + ( , + & ht68f40 special purpose data memory ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 31 october 24, 2011 , , & , / & , 1 & , 4 & , 6 & , 7 & , 8 & , 9 & , ! & , = & , + & , 0 & , & , * & , & , & / , & / / & / 1 & / 4 & / 6 & / 7 & / 8 & / 9 & / ! & / = & / + & / 0 & / & / * & / & / & 1 , & 1 / & 1 1 & 1 4 & 1 6 & 1 7 & 1 8 & 1 9 & 1 ! & 1 = & 1 + & 1 0 & 1 & 1 * & 1 & 1 & 4 , & 4 / & 4 1 & 4 4 & 4 6 & 4 7 & 4 8 & 4 9 & 4 ! & 4 = & 4 + & 4 0 & 4 & 4 * & 4 & 4 & 6 , & 6 / & 6 1 & 6 4 & 6 6 & 6 7 & 6 8 & 6 9 & 6 ! & 6 = & 6 + & 6 0 & 6 & 6 * & 6 & 6 & 7 , & 7 / & 7 1 & 7 4 & 7 6 & 7 7 & 7 8 & 7 9 & 7 ! & 7 = & 7 + & 7 0 & 7 & 7 * & 7 & 7 & 8 , & 8 / & 8 1 & 8 4 & 8 6 & 8 7 & 8 8 & 8 9 & 8 ! & 8 = & 8 + & 8 0 & 8 & 8 * & 8 & 8 & 9 , & 9 / & 9 1 & 9 4 & 9 6 & 9 7 & 9 8 & 9 9 & 9 ! & 9 = & 9 + & 9 0 & 9 & 9 * & 9 & 9 & " # $ % % % % " # $ % % % " # $ $ + * , / , / 1 / , / / / 1 / * ( / * & / + ( / + & / 0 ( / 0 & 1 , 1 / 1 * ( 1 * & 1 + ( 1 + & 1 4 , 4 / 4 * ( 4 * & 4 + ( 4 + & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ + , , + / / 0 + ( 0 ( 0 ( & 0 & + $ * ( . * 5 > * 0 5 , 5 / 5 1 5 4 , / 1 4 + $ + $ + + 0 $ 0 0 $ * $ * * $ $ > $ > > $ $ $ $ $ $ , / , / * + 1 , , , / , * ( , * & , + ( , + & ht68f60 special purpose data memory , , & , / & , 1 & , 4 & , 6 & , 7 & , 8 & , 9 & , ! & , = & , + & , 0 & , & , * & , & , & / , & / / & / 1 & / 4 & / 6 & / 7 & / 8 & / 9 & / ! & / = & / + & / 0 & / & / * & / & / & 1 , & 1 / & 1 1 & 1 4 & 1 6 & 1 7 & 1 8 & 1 9 & 1 ! & 1 = & 1 + & 1 0 & 1 & 1 * & 1 & 1 & 4 , & 4 / & 4 1 & 4 4 & 4 6 & 4 7 & 4 8 & 4 9 & 4 ! & 4 = & 4 + & 4 0 & 4 & 4 * & 4 & 4 & 6 , & 6 / & 6 1 & 6 4 & 6 6 & 6 7 & 6 8 & 6 9 & 6 ! & 6 = & 6 + & 6 0 & 6 & 6 * & 6 & 6 & 7 , & 7 / & 7 1 & 7 4 & 7 6 & 7 7 & 7 8 & 7 9 & 7 ! & 7 = & 7 + & 7 0 & 7 & 7 * & 7 & 7 & 8 , & 8 / & 8 1 & 8 4 & 8 6 & 8 7 & 8 8 & 8 9 & 8 ! & 8 = & 8 + & 8 0 & 8 & 8 * & 8 & 8 & 9 , & 9 / & 9 1 & 9 4 & 9 6 & 9 7 & 9 8 & 9 9 & 9 ! & 9 = & 9 + & 9 0 & 9 & 9 * & 9 & 9 & " # $ % % " # $ % " # $ $ + * , / , / 1 / , / / / 1 / * ( / * & / + ( / + & / 0 ( / 0 & 1 , 1 / 1 * ( 1 * & 1 + ( 1 + & 1 4 , 4 / 4 * ( 4 * & 4 + ( 4 + & $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ + , , + / / 0 + ( 0 ( 0 ( & 0 & + $ * ( . * 5 > * 0 5 , 5 / 5 1 $ , / 1 4 + $ + $ + + 0 $ 0 0 $ * $ * * $ $ $ $ $ $ $ $ $ $ $ , / , / * + 1 , , , / , * ( , * & , + ( , + & ht68f50 special purpose data memory ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 32 october 24, 2011 the second area of data memory is known as the gen - eral purpose data memory, which is reserved for gen - eral purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into several banks, the structure of which depends upon the device chosen. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the different data memory banks is achieved by setting the bank pointer to the cor - rect value. the start address of the data memory for all devices is the address 00h. special function register description most of the special function register details will be de - scribed in the relevant functional section, however sev - eral registers require a separate description in this section. indirect addressing registers iar0, iar1 the indirect addressing registers, iar0 and iar1, al - though having their locations in normal ram register space, do not actually physically exist as normal regis - ters. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory ad- dressing, where the actual memory address is speci- fied. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corre- sponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect ad - dressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no op - eration. memory pointers mp0, mp1 two memory pointers, known as mp0 and mp1 are pro - vided. these memory pointers are physically imple - mented in the data memory and can be manipulated in the same way as normal registers providing a conve - nient way with which to address and track data. when any operation to the relevant indirect addressing regis - ters is carried out, the actual address that the microcontroller is directed to, is the address specified by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct ad - dressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. note that for the ht68f20 and ht68f30 devices, bit 7 of the memory pointers is not required to address the full memory space. when bit 7 of the memory pointers for ht68f20 and ht68f30 devices is read, a value of 1 will be returned. the following example shows how to clear a section of four data memory locations already defined as loca- tions adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific ram addresses. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 33 october 24, 2011 bank pointer bp depending upon which device is used, the program and data memory are divided into several banks. selecting the required program and data memory area is achieved using the bank pointer. bit 5 of the bank pointer is used to select program memory bank 0 or 1, while bits 0~2 are used to select data memory banks 0~4. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being ac - cessed irrespective of the value of the bank pointer. ac - cessing data from banks other than bank 0 must be implemented using indirect addressing. as both the program memory and data memory share the same bank pointer register, care must be taken during programming. device bit 76543210 ht68f20 ht68f40 dmbp0 ht68f30 ht68f50 dmbp1 dmbp0 ht68f60 pmbp0 dmbp2 dmbp1 dmbp0 bp registers list bp register ht68f20/ht68f40 bit76543210 name dmbp0 r/w r/w por 0 bit7~1 unimplemented, read as 0 bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 ht68f30/ht68f50 bit76543210 name dmbp1 dmbp0 r/w r/w r/w por 00 bit7~2 unimplemented, read as 0 bit1~0 dmbp1, dmbp0 : select data memory banks 00: bank 0 01: bank 1 10: bank 2 11: undefined ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 34 october 24, 2011 ht68f60 bit76543210 name pmbp0 dmbp2 dmbp1 dmbp0 r/w r/w r/w r/w r/w por 0 000 bit7~6 unimplemented, read as 0 bit 5 pmbp0 : select program memory banks 0: bank 0, program memory address is from 0000h ~ 1fffh 1: bank 1, program memory address is from 2000h ~ 2fffh bit4~3 unimplemented, read as 0 bit2~0 dmbp2 ~ dmbp0 : select data memory banks 000: bank 0 001: bank 1 010: bank 2 011: bank 3 100: bank 4 101~111: undefined accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per - mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tbhp, tblh these three special function registers are used to con - trol operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer and indicates the location where the table data is lo - cated. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, al - lowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been exe - cuted. note that the lower order table data byte is trans - ferred to a user defined location. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage- ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib - ble into the low nibble in subtraction; otherwise ac is cleared. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 35 october 24, 2011 z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high - est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit76543210 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 00xxxx x unknown bit 7, 6 unimplemented, read as 0 bit 5 to : watchdog time-out flag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down flag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero flag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 36 october 24, 2011 eeprom data memory the device contains an area of internal eeprom data memory. eeprom, which stands for electrically eras - able programmable read only memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows in - formation such as product identification numbers, cali - bration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity varies from 32x8 to 256 8 bits, according to the device selected. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an address and data regis - ter in bank 0 and a single control register in bank 1. device capacity address ht68f20 328 00h ~ 1fh ht68f30 648 00h ~ 3fh ht68f40 1288 00h ~ 7fh ht68f50/ht68f60 2568 00h ~ ffh eeprom registers three registers control the overall operation of the inter - nal eeprom data memory. these are the address reg - ister, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are lo - cated in bank 0, they can be directly accessed in the same was as any other special function register. the eec register however, being located in bank1, cannot be directly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must first be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are executed. eeprom register list ht68f20 name bit 76543210 eea d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd ht68f30 name bit 76543210 eea d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd ht68f40 name bit 76543210 eea d6 d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 37 october 24, 2011 ht68f50/ht68f60 name bit 76543210 eea d7 d6 d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd eea register ht68f20 bit76543210 name d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w por xxxxx x unknown bit7~5 unimplemented, read as 0 bit4~0 data eeprom address data eeprom address bit 4 ~ bit 0 ht68f30 bit76543210 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por xxxxxx x unknown bit7~6 unimplemented, read as 0 bit5~0 data eeprom address data eeprom address bit 5 ~ bit 0 ht68f40 bit76543210 name d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por xxxxxxx x unknown bit 7 unimplemented, read as 0 bit6~0 data eeprom address data eeprom address bit 6 ~ bit 0 ht68f50/ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxxx x unknown bit7~0 data eeprom address data eeprom address bit 7 ~ bit 0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 38 october 24, 2011 eec register bit76543210 name wren wr rden rd r/w r/w r/w r/w r/w por 0000 bit7~4 unimplemented, read as 0 bit 3 wren : data eeprom write enable 0: disable 1: enable this is the data eeprom write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: write cycle has finished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has finished. setting this bit high will have no effect if the wren has not first been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has finished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has finished. setting this bit high will have no effect if the rden has not first been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must first be set high to en - able the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initi - ate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be auto - matically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is exe - cuted. the application program can poll the rd bit to de - termine when the data is valid for reading. writing data to the eeprom to write data to the eeprom, the write enable bit, wren, in the eec register must first be set high to en - able the write function. the eeprom address of the data to be written must then be placed in the eea regis - ter and the data placed in the eed register. if the wr bit in the eec register is now set high, an internal write cy - cle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has finished can be im - plemented either by polling the wr bit in the eec regis - ter or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to de - termine when the write cycle has ended. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 39 october 24, 2011 write protection protection against inadvertent write operation is pro - vided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write opera - tions. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write or read interrupt is generated when an eeprom write or read cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function inter - rupt request flag will both be set. if the global, eeprom and multi-function interrupts are enabled and the stack is not full, a jump to the associated multi-function inter - rupt vector will take place. when the interrupt is serviced only the multi-function interrupt flag will be automatically reset, the eeprom interrupt flag must be manually re - set by the application program. more details can be ob - tained in the interrupt section. programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensur - ing that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be nor - mally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. al - though certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. programming examples reading data from the eeprom - polling method mov a, eeprom_adres ; user defined address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr bp mov a, eedata ; move read data to register mov read_data, a writing data to the eeprom polling method mov a, eeprom_adres ; user defined address mov eea, a mov a, eeprom_data ; user defined data mov eed, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr bp ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 40 october 24, 2011 oscillator various oscillator options offer the user a wide range of functions according to their various application require - ments. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of configuration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watch - dog timer and time base interrupts. external oscilla - tors requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power re - quirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dy - namically switching between fast and slow system clock, the device has the flexibility to optimize the perfor - mance/power ratio, a feature especially important in power sensitive portable applications. type name freq. pins external crystal hxt 400khz~ 20mhz osc1/ osc2 external rc erc 8mhz osc1 internal high speed rc hirc 4, 8 or 12mhz external low speed crystal lxt 32.768khz xt1/ xt2 internal low speed rc lirc 32khz oscillator types system clock configurations there are five methods of generating the system clock, three high speed oscillators and two low speed oscilla - tors. the high speed oscillators are the external crystal/ ceramic oscillator, external rc network oscillator and the internal 4mhz, 8mhz or 12mhz rc oscillator. the two low speed oscillators are the internal 32khz rc os - cillator and the external 32.768khz crystal oscillator. se - lecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. hxt erc hirc lirc lxt 6-stage prescaler high speed oscillation low speed oscillation low speed oscillation configuration option high s pe ed oscillation configuration option f h f h /2 f h /4 f h /8 f h /16 f h /32 f h /64 f l hlclk, cks2~cks0 bits fas t wake-up from s le ep mode or idle mode control (for hxt only) f sy s f sub system clock configurations ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 41 october 24, 2011 the actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. external crystal/ ceramic oscillator hxt the external crystal/ ceramic system oscillator is one of the high frequency oscillator choices, which is se - lected via configuration option. for most crystal oscilla - tor configurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requir - ing external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be neces - sary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer s specification. crystal oscillator c1 and c2 values crystal frequency c1 c2 12mhz 0pf 0pf 8mhz 0pf 0pf 4mhz 0pf 0pf 1mhz 100pf 100pf note: c1 and c2 values are for guidance only. crystal recommended capacitor values external rc oscillator erc using the erc oscillator only requires that a resistor, with a value between 56k and 2.4m , is connected between osc1 and vdd, and a capacitor is connected between osc1 and ground, providing a low cost oscilla - tor configuration. it is only the external resistor that de - termines the oscillation frequency; the external capacitor has no influence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to en - sure that the influence of the power supply voltage, tem - perature and process variations on the oscillation frequency are minimised. as a resistance/frequency ref - erence point, it can be noted that with an external 120k resistor connected and with a 5v voltage power supply and temperature of 25 c degrees, the oscillator will have a frequency of 8mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pb1, leaving pin pb2 free for use as a normal i/o pin. internal rc oscillator hirc the internal rc oscillator is a fully integrated system os- cillator requiring no external components. the internal rc oscillator has three fixed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal fre- quency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25 c degrees, the fixed os - cillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pb1 and pb2 are free for use as normal i/o pins. external 32.768khz crystal oscillator lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is se - lected via configuration option. this clock source has a fixed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscil - lation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manu - facturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. external rc oscillator erc ! ! ! " # $ # # % & # ' ! ( crystal/resonator oscillator hxt ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 42 october 24, 2011 when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. how - ever, in many microcontroller applications it may be nec - essary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the ex - act values of c1 and c2 should be selected in consulta - tion with the crystal or resonator manufacturer s specification. the external parallel feedback resistor, rp, is required. some configuration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins. lxt oscillator c1 and c2 values crystal frequency c1 c2 32.768khz 10pf 10pf note: 1. c1 and c2 values are for guidance only. 2. r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 quick start 1 low-power after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. how - ever, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the appli - cation program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always func - tion normally, the only difference is that it will take more time to start up if in the low-power mode. internal 32khz oscillator lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via con- figuration option. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to en - sure that the influence of the power supply voltage, tem - perature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 c degrees, the fixed oscillation frequency of 32khz will have a tolerance within 10%. supplementary oscillators the low speed oscillators, in addition to providing a sys - tem clock source are also used to provide a clock source to two other device functions. these are the watchdog timer and the time base interrupts. ) ! ! " # $ # # % # ' ! ( * + ( , - . / 0 1 1 external lxt oscillator ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 43 october 24, 2011 operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in bat - tery powered portable applications. the fast clocks re - quired for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best perfor - mance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using config - uration options and register programming, a clock sys - tem can be configured to obtain maximum application performance. the main system clock, can come from either a high fre - quency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either an hxt, erc or hirc oscillator, selected via a configuration option. the low speed system clock source can be sourced from internal clock f l .iff l is se - lected then it can be sourced by either the lxt or lirc oscillators, selected via a configuration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the periph - eral circuits, the substitute clock, f sub , and the time base clock, f tbc . each of these internal clocks are sourced by either the lxt or lirc oscillators, selected via configuration options. the f sub clock is used to pro - vide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. f tb c f sys / 4 tbck f sub f sys/ 4 f tb f s configuration option tim e b ase wdt hxt erc hirc lirc lxt 6- st age p res caler high speed oscillation low speed oscillation low speed oscillation configuration option high speed oscillation configuration option f h f h /2 f h /4 f h /8 f h /16 f h /32 f h /6 4 f l hlclk, cks2~cks0 bits fast wake-up from sleep mode or idle mode control (for hxt only) f sys f sub system clock configurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 44 october 24, 2011 together with f sys /4 it is also used as one of the clock sources for the watchdog timer. the f tbc clock is used as a source for the time base interrupt functions and for the tms. system operation modes there are six different modes of operation for the microcontroller, each one with its own special character - istics and which can be chosen according to the specific performance and power requirements of the applica - tion. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f sub f s f tbc normal mode on f h ~f h /64 on on on slow mode on f l on on on idle0 mode off off on on/off on idle1 mode off on on on on sleep0 mode off off off off off sleep1 mode off off on on off normal mode as the name suggests this is one of the main operat - ing modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt, erc or hirc oscillators. the high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed os- cillator is used, running the microcontroller at a di - vided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller oper - ates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an halt instruc - tion is executed and when the idlen bit in the smod register is low. in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to 0 . if the lvden is set to 1 ,itwon t enter the sleep0 mode. sleep1 mode the sleep mode is entered when an halt instruc - tion is executed and when the idlen bit in the smod register is low. in the sleep1 mode the cpu will be stopped. however the f sub and f s clocks will continue to operate if the lvden is 1 or the watchdog timer function is enabled and if its clock source is chosen via configuration option to come from the f sub . idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod reg- ister is high and the fsyson bit in the wdtc register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watch- dog timer, tms and sim. in the idle0 mode, the sys- tem oscillator will be stopped. in the idle0 mode the watchdog timer clock, f s , will either be on or off de - pending upon the f s clock source. if the source is f sys /4 then the f s clock will be off, and if the source co - mes from f sub then f s will be on. idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod reg - ister is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral func - tions operational such as the watchdog timer, tms and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the watchdog timer clock, f s , will be on. if the source is f sys /4 then the f s clock will be on, and if the source comes from f sub then f s will be on. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 45 october 24, 2011 control register a single register, smod, is used for overall control of the internal clocks within the device. smod register b i t76543210 name cks2 cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 00000011 bit 7~5 cks2~cks0 : the system clock selection when hlclk is 0 000: f l (f lxt or f lirc ) 001: f l (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten : fast wake-up control (only for hxt) 0: disable 1: enable this is the fast wake-up control bit which determines if the f sub clock source is initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temporary system clock to provide a faster wake up time as the f sub clock is available. bit 3 lto : low speed system oscillator ready flag 0: not ready 1: ready this is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the flag will be low when in the sleep0 mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 hto : high speed system oscillator ready flag 0: not ready 1: ready this is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. this flag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this flag will always be read as 1 by the application program after device power-on. the flag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the erc or hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 46 october 24, 2011 fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the lxt or lirc oscillator, to act as a tem - porary clock to first drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast wake-up function has no effect because the f sub clock is stopped. the fast wake-up enable/dis - able function is controlled using the fsten bit in the smod register. if the hxt oscillator is selected as the normal mode system clock, and if the fast wake-up function is en - abled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the hto flag will switch high and the system will switch over to operating from the hxt oscillator. if the erc or hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock cy - cles of the erc or hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no effect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 1024 hxt cycles 1024 hxt cycles 1~2 hxt cycles 1 1024 hxt cycles 1~2 f sub cycles (system runs with f sub first for 1024 hxt cycles and then switches over to run with the hxt clock) 1~2 hxt cycles erc x 15~16 erc cycles 15~16 erc cycles 1~2 erc cycles hirc x 15~16 hirc cycles 15~16 hirc cycles 1~2 hirc cycles lirc x 1~2 lirc cycles 1~2 lirc cycles 1~2 lirc cycles lxt x 1024 ltx cycles 1024 lxt cycles 1~2 lxt cycles wake-up times note that if the watchdog timer is disabled, which means that the lxt and lirc are all both off, then there will be no fast wake-up function available when the device wakes-up from the sleep0 mode. / " 2 3 ! 4 5 6 * 2 7 8 9 6 9 : ; 2 4 8 / < / & , = / 5 6 4 9 6 9 / " 2 3 ! 5 6 * 2 7 8 4 8 4 9 6 9 / " 2 3 ! 5 6 * 2 7 8 4 8 4 9 6 9 4 8 2 2 5 6 4 9 6 9 / / " 2 3 ! 4 5 6 * 2 7 8 9 6 9 : 2 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 47 october 24, 2011 operating mode switching and wake-up the device can switch between operating modes dy - namically allowing the user to select the best perfor - mance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruc - tion. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is de - termined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when the hlclk bit switches to a low level, which im - plies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l .if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the op - eration of other internal functions such as the tms and the sim. the accompanying flowchart shows what hap - pens when the device moves between the various oper - ating modes. normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000 or 001 in the smod regis - ter. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high per - formance and can subsequently reduce power con - sumption. the slow mode is sourced from the lxt or the lirc oscillators and therefore requires these oscillators to be stable before full mode switching occurs. this is moni - tored using the lto bit in the smod register. 2 : > ! 2 7 7 5 > ! 2 7 7 5 > ! * 7 2 > ! * 2 7 > ! > " 2 > ! ? < ? 8 3 9 ; / 2 2 ? 8 : ! 2 * 2 7 8 / " 2 3 ! : 2 * 2 7 8 / " 2 3 ! * 2 7 8 ) 4 8 / " 2 3 ! * 2 7 8 ) 4 8 / " 2 3 ! ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 48 october 24, 2011 > " 2 > ! 2 7 7 5 > ! 2 7 7 5 > ! * 2 7 > ! * 2 7 > ! 2 : > ! ? < ? 9 ) 9 / 2 2 ? 8 / 2 2 ? 8 : ! 2 * 2 7 8 / " 2 3 ! : 2 * 2 7 8 / " 2 3 ! * 2 7 8 ) 4 8 / " 2 3 ! * 2 7 8 ) 4 8 / " 2 3 ! slow mode to normal mode switching in slow mode the system uses either the lxt or lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0 , but cks2~cks0 is set to 010, 011, 100, 101, 110 or 111 . as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the halt instruc- tion in the application program with the idlen bit in smod register equal to 0 and the wdt and lvd both off. when this instruction is executed under the condi - tions described above, the following will occur: the system clock, wdt clock and time base clock will be stopped and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 49 october 24, 2011 entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 0 and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: the system clock and time base clock will be stopped and the application program will stop at the halt instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock as the wdt is enabled. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in wdtc register equal to 0 . when this instruction is executed under the condi- tions described above, the following will occur: the system clock will be stopped and the application program will stop at the halt instruction, but the time base clock and f sub clock will be on. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the halt instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in wdtc register equal to 1 . when this instruction is executed under the with conditions described above, the following will occur: the system clock and time base clock and f sub clock will be on and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt is enabled regardless of the wdt clock source which originates from the f sub clock or from the system clock. the i/o ports will maintain their present conditions. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are con - nected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum cur - rent is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the sys - tem oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 50 october 24, 2011 wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as fol - lows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup using the pawu regis - ter to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the pro - gram will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possible situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fi- nally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular inter - rupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the hxt and lxt oscillators both use the same sst counter. for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an off state. the lxt oscillator uses the sst counter after hxt oscillator has finished its sst period. if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute first in - struction after hto is 1 . at this time, the lxt oscilla - tor may not be stability if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the first instruction is executed. if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is 1 , the system clock can be switched to the lxt or lirc oscillator after wake up. there are peripheral functions, such as wdt, tms and sim, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change ac - cordingly. the on/off condition of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub . ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 51 october 24, 2011 watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown lo - cations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the in - ternal clock, f s , which is in turn supplied by one of two sources selected by configuration option: f sub or f sys /4. the f sub clock can be sourced from either the lxt or lirc oscillators, again chosen via a configuration op - tion. the watchdog timer source clock is then subdi - vided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specified internal clock period can vary with vdd, temperature and pro - cess variations. the lxt oscillator is supplied by an ex - ternal 32.768khz crystal. the other watchdog timer clock source option is the f sys /4 clock. the watchdog timer clock source can originate from its own internal lirc oscillator, the lxt oscillator or f sys /4. it is divided by a value of 2 8 to 2 15 , using the ws2~ws0 bits in the wdtc register to obtain the required watchdog timer time-out period. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. this reg - ister together with several configuration options control the overall operation of the watchdog timer. wdtc register bit76543210 name fsyson ws2 ws1 ws0 wdten3 wdten2 wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por01111010 bit 7 fsyson: f sys control in idle mode 0: disable 1: enable bit6~4 ws2, ws1, ws0 : wdt time-out period selection 000: 256/f s 001: 512/f s 010: 1024/f s 011: 2048/f s 100: 4096/f s 101: 8192/f s 110: 16384/f s 111: 32768/f s these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period. bit3~0 wdten3, wdten2, wdten1, wdten0 : wdt software control 1010: disable other: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 52 october 24, 2011 - @ $ ' ! : @ a - & < b & c & - : 5 - @ @ > 6 1 : $ 2 : $ 2 : $ * 2 6 9 : < : a & - < & b c > 6 1 4 & = > 6 1 2 1 2 * $ $ watchdog timer watchdog timer operation the watchdog timer operates by providing a device re - set when its timer overflows. this means that in the ap - plication program and during normal operation the user has to strategically clear the watchdog timer before it overflows to prevent the watchdog timer from execut - ing a reset. this is done using the clear watchdog in - structions. if the program malfunctions for whatever reason, jumps to an unkown location, or enters an end - less loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overflow and reset the device. some of the watch - dog timer options, such as enable/disable, clock source selection and clear instruction type are selected using configuration options. in addition to a configuration op - tion to enable/disable the watchdog timer, there are also four bits, wdten3~wdten0, in the wdtc regis - ter to offer an additional enable/disable control of the watchdog timer. to disable the watchdog timer, as well as the configuration option being set to disable, the wdten3~wdten0 bits must also be set to a specific value of 1010 . any other values for these bits will keep the watchdog timer enabled, irrespective of the configu - ration enable/disable setting. after power on these bits will have the value of 1010. if the watchdog timer is used it is recommended that they are set to a value of 0101 for maximum noise immunity. note that if the watchdog timer has been disabled, then any instruction relating to its operation will result in no operation. wdt configuration option wdten3~ wdten0 bits wdt wdt enable xxxx enable wdt disable except 1010 enable wdt disable 1010 disable watchdog timer enable/disable control under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the first is an external hardware reset, which means a low level on the res pin, the second is using the watchdog timer software clear instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by configuration option. the first option is to use the sin - gle clr wdt instruction while the second is to use the two commands clr wdt1 and clr wdt2 . for the first option, a simple execution of clr wdt will clear the wdt while for the second option, both clr wdt1 and clr wdt2 must both be executed alter - nately to successfully clear the watchdog timer. note that for this second option, if clr wdt1 is used to clear the watchdog timer, successive executions of this instruction will have no effect, only the execution of a clr wdt2 instruction will clear the watchdog timer. similarly after the clr wdt2 instruction has been ex - ecuted, only a successive clr wdt1 instruction can clear the watchdog timer. the maximum time out period is when the 2 15 division ra- tio is selected. as an example, with a 32.768khz lxt oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. if the f sys /4 clock is used as the watchdog timer clock source, it should be noted that when the system enters the sleep or idle0 mode, then the instruction clock is stopped and the watchdog timer may lose its protecting purposes. for systems that operate in noisy environments, using the f sub clock source is strongly recommended. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 53 october 24, 2011 reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force - fully pulled low. in such a case, known as a normal oper - ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer over- flows and resets the microcontroller . all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller . as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. res pin as the reset pin is shared with pb.0, the reset function must be selected using a configuration option. al - though the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir - cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. 5 9 & 7 < . < . d d = = - d + d note: * it is recommended that this component is added for added esd protection ** it is recommended that this component is added in environments where power line noise is significant external res circuit 7 * e f f note: t rstd is power-on delay, typical time=100ms power-on reset timing chart ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 54 october 24, 2011 pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. low voltage reset lvr the microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the bat - tery, the lvr will automatically reset the device inter - nally. the lvr includes the following specifications: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specified in the a.c. characteristics. if the low voltage state does not exceed t lvr , the lvr will ig - nore it and will not perform a reset function. one of a range of specified voltage values for v lvr can be se - lected using configuration options. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera- tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1. watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset uu res or lvr reset during normal or slow mode operation 1u wdt time-out reset during normal or slow mode operation 11 wdt time-out reset during idle or sleep mode operation note: u stands for unchanged the following table indicates the way in which the vari- ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off input/output ports i/o ports will be setup as inputs. stack pointer stack pointer will point to the top of the stack f : @ * note: t rstd is power-on delay, typical time=100ms wdt time-out reset during normal operation timing chart : @ * wdt time-out reset during sleep or idle timing chart 2 * f note: t rstd is power-on delay, typical time=100ms low voltage reset timing chart 7 * e = f note: t rstd is power-on delay, typical time=100ms res reset timing chart ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 55 october 24, 2011 the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will reflect the situation for the larger package type. ht68f20 register register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxx xxxx xxx xxxx xxx xxxx uuu uuuu mp1 xxx xxxx xxx xxxx xxx xxxx uuu uuuu bp 0 0 0 u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xx xxxx uu uuuu uu uuuu uu uuuu tbhp xx uu uu uu status 00 xxxx uu uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc 00 000 00 000 00 000 uu uuu integ 0000 0000 0000 uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu intc0 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 00 00 00 00 00 00 uu uu mfi1 00 00 00 00 00 00 uu uu mfi2 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 00 0000 00 0000 00 0000 uu uuuu pb 11 1111 11 1111 11 1111 uu uuuu pbc 11 1111 11 1111 11 1111 uu uuuu pcpu 0000 0000 0000 uuuu pc 1111 1111 1111 uuuu pcc 1111 1111 1111 uuuu cp0c 1000 0 1 1000 0 1 1000 0 1 uuuu uu cp1c 1000 0 1 1000 0 1 1000 0 1 uuuu uu simc0 1110 000 1110 000 1110 000 uuuu uuu ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 56 october 24, 2011 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 00 00 00 uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 00 00 00 uu eea x xxxx x xxxx x xxxx 0 0000 eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec 0000 0000 0000 uuuu tmpc0 01 1 01 1 01 1 uu u tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh 00 00 00 uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah 00 00 00 uu scomc 0000 0000 0000 0000 0000 0000 uuuu uuuu note: u stands for unchanged x stands for unknown stands for unimplemented ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 57 october 24, 2011 ht68f30 register register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxx xxxx xxx xxxx xxx xxxx uuu uuuu mp1 xxx xxxx xxx xxxx xxx xxxx uuu uuuu bp 00 00 00 uu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xx xxxx uu uuuu uu uuuu uu uuuu tbhp xxx uuu uuu uuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc 00 000 00 000 00 000 uu uuu integ 0000 0000 0000 uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu intc0 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 00 00 00 00 00 00 uu uu mfi1 000 000 000 000 000 000 uuu uuu mfi2 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 00 0000 00 0000 00 0000 uu uuuu pb 11 1111 11 1111 11 1111 uu uuuu pbc 11 1111 11 1111 11 1111 uu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu cp0c 1000 0 1 1000 0 1 1000 0 1 uuuu uu cp1c 1000 0 1 1000 0 1 1000 0 1 uuuu u u simc0 1110 000 1110 000 1110 000 uuuu uuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 58 october 24, 2011 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 00 00 00 uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 00 00 00 uu eea xx xxxx xx xxxx xx xxxx uu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec 0000 0000 0000 uuuu tmpc0 1 01 01 1 01 01 1 01 01 u uu uu prm0 000 000 000 uuu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh 00 00 00 uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah 00 00 00 uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh 00 00 00 uu scomc 0000 0000 0000 0000 0000 0000 uuuu uuuu note: u stands for unchanged x stands for unknown stands for unimplemented ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 59 october 24, 2011 ht68f40 register register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp 0 0 0 u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxx xxxx uuu uuuu uuu uuuu uuu uuuu tbhp xxxx uuuu uuuu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc 00 000 00 000 00 000 uu uuu integ 0000 0000 0000 uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu intc0 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 000 000 000 000 000 000 uuu uuu mfi2 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu 00 00 00 uu pf 11 11 11 uu pfc 11 11 11 uu ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 60 october 24, 2011 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) cp0c 1000 0 1 1000 0 1 1000 0 1 uuuu uu cp1c 1000 0 1 1000 0 1 1000 0 1 uuuu uu simc0 1110 000 1110 000 1110 000 uuuu uuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 00 00 00 uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 00 00 00 uu eea xxx xxxx xxx xxxx xxx xxxx uuu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec 0000 0000 0000 uuuu tmpc0 1001 01 1001 01 1001 01 uuuu uu tmpc1 01 01 01 uu prm0 0 0 0000 0 0 0000 0 0 0000 u u uuuu prm1 000 0000 000 0000 000 0000 uuu uuuu prm2 00 0000 00 0000 00 0000 uu uuuu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh 00 00 00 uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah 00 00 00 uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh 00 00 00 uu tm2c0 0000 0 0000 0 0000 0 uuuu u tm2c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2rp 0000 0000 0000 0000 0000 0000 uuuu uuuu scomc 0000 0000 0000 0000 0000 0000 uuuu uuuu note: u stands for unchanged x stands for unknown stands for unimplemented ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 61 october 24, 2011 ht68f50 register register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp 00 00 00 uu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp x xxxx u uuuu u uuuu u uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc 00 000 00 000 00 000 uu uuu integ 0000 0000 0000 uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu intc0 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 000 000 000 000 000 000 uuu uuu mfi2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi3 00 00 00 00 00 00 uu uu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu 00 00 00 uu pf 11 11 11 uu pfc 11 11 11 uu cp0c 1000 0 1 1000 0 1 1000 0 1 uuuu uu cp1c 1000 0 1 1000 0 1 1000 0 1 uuuu uu simc0 1110 000 1110 000 1110 000 uuuu uuu ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 62 october 24, 2011 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 00 00 00 uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 00 00 00 uu eea xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec 0000 0000 0000 uuuu tmpc0 1001 01 1001 01 1001 01 uuuu uu tmpc1 01 01 01 01 01 01 uu uu prm0 0 0 0000 0 0 0000 0 0 0000 u u uuuu prm1 000 0000 000 0000 000 0000 uuu uuuu prm2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh 00 00 00 uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah 00 00 00 uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh 00 00 00 uu tm2c0 0000 0 0000 0 0000 0 uuuu u tm2c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2rp 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dh 00 00 00 uu tm3al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3ah 00 00 00 uu scomc 0000 0000 0000 0000 0000 0000 uuuu uuuu note: u stands for unchanged x stands for unknown stands for unimplemented ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 63 october 24, 2011 ht68f60 register register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu bp 0 000 0 000 0 000 u uuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp xx xxxx uu uuuu uu uuuu uu uuuu status 00 xxxx uu uuuu 1u uuuu 11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu lvdc 00 000 00 000 00 000 uu uuu integ 0000 0000 0000 0000 0000 0000 uuuu uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu intc0 000 0000 000 0000 000 0000 uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 uuuu uuuu intc3 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 000 000 000 000 000 000 uuu uuu mfi2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi3 00 00 00 00 00 00 uu uu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pfpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pf 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 uuuu uuuu pgpu 00 0000 0000 0000 0000 uuuu uuuu pg 11 11 11 uu pgc 11 11 11 uu ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 64 october 24, 2011 register reset (power-on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) cp0c 1000 0 1 1000 0 1 1000 0 1 uuuu uu cp1c 1000 0 1 1000 0 1 1000 0 1 uuuu uu simc0 1110 000 1110 000 1110 000 uuuu uuu simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh 00 00 00 uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah 00 00 00 uu eea xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eed xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu eec 0000 0000 0000 uuuu tmpc0 1001 01 1001 01 1001 01 uuuu uu tmpc1 01 01 01 01 01 01 uu uu prm0 0000 0000 0000 0000 0000 0000 uuuu uuuu prm1 0000 0000 0000 0000 0000 0000 uuuu uuuu prm2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh 00 00 00 uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah 00 00 00 uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh 00 00 00 uu tm2c0 0000 0 0000 0 0000 0 uuuu u tm2c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2rp 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dh 00 00 00 uu tm3al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3ah 00 00 00 uu scomc 0000 0000 0000 0000 0000 0000 uuuu uuuu note: u stands for unchanged x stands for unknown stands for unimplemented ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 65 october 24, 2011 input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa~pg. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m denotes the port address. for output opera - tion, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list ht68f20 register name bit 76543210 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pbpu d5 d4 d3 d2 d1 d0 pb d5 d4 d3 d2 d1 d0 pbc d5 d4 d3 d2 d1 d0 pcpu d3 d2 d1 d0 pc d3 d2 d1 d0 pcc d3 d2 d1 d0 ht68f30 register name bit 76543210 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pbpu d5 d4 d3 d2 d1 d0 pb d5 d4 d3 d2 d1 d0 pbc d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 66 october 24, 2011 ht68f40/ht68f50 register name bit 76543210 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pbpu d7 d6 d5 d4 d3 d2 d1 d0 pb d7 d6 d5 d4 d3 d2 d1 d0 pbc d7 d6 d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 pdpu d7 d6 d5 d4 d3 d2 d1 d0 pd d7 d6 d5 d4 d3 d2 d1 d0 pdc d7 d6 d5 d4 d3 d2 d1 d0 pepu d7 d6 d5 d4 d3 d2 d1 d0 pe d7 d6 d5 d4 d3 d2 d1 d0 pec d7 d6 d5 d4 d3 d2 d1 d0 pfpu d1 d0 pf d1 d0 pfc d1 d0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 67 october 24, 2011 ht68f60 register name bit 76543210 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pbpu d7 d6 d5 d4 d3 d2 d1 d0 pb d7 d6 d5 d4 d3 d2 d1 d0 pbc d7 d6 d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 pdpu d7 d6 d5 d4 d3 d2 d1 d0 pd d7 d6 d5 d4 d3 d2 d1 d0 pdc d7 d6 d5 d4 d3 d2 d1 d0 pepu d7 d6 d5 d4 d3 d2 d1 d0 pe d7 d6 d5 d4 d3 d2 d1 d0 pec d7 d6 d5 d4 d3 d2 d1 d0 pfpu d7 d6 d5 d4 d3 d2 d1 d0 pf d7 d6 d5 d4 d3 d2 d1 d0 pfc d7 d6 d5 d4 d3 d2 d1 d0 pgpu d1 d0 pg d1 d0 pgc d1 d0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 68 october 24, 2011 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external re - sistor. to eliminate the need for these external resistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu~pgpu, and are implemented using weak pmos transistors. papu register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 pbpu register ht68f40/ht68f50/ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 pcpu register ht68f30/ht68f40/ht68f50/ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 pdpu register ht68f40/ht68f50/ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 pepu register ht68f40/ht68f50/ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 69 october 24, 2011 pfpu register ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 i/o port bit 7 ~ bit 0 pull-high control 0: disable 1: enable pbpu register ht68f20/ht68f30 bit76543210 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 000000 bit 7~6 unimplemented, read as 0 bit 5~0 pbpu : port b bit 5 ~ bit 0 pull-high control 0: disable 1: enable pcpu register ht68f20 bit76543210 name d3 d2 d1 d0 r/w r/w r/w r/w r/w por 0000 bit 7~4 unimplemented, read as 0 bit 3~0 pcpu : port c bit 3 ~ bit 0 pull-high control 0: disable 1: enable pfpu register ht68f40/ht68f50 bit76543210 name d1 d0 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 pfpu : port f bit 1 ~ bit 0 pull-high control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 70 october 24, 2011 pgpu register ht68f60 bit76543210 name d1 d0 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 pgpu : port g bit 1 ~ bit 0 pull-high control 0: disable 1: enable port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register b i t76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o r00000000 bit 7~0 pawu : port a bit 7 ~ bit 0 wake-up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as pac~pgc, to control the input/output configuration. with this con- trol register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corre- sponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be di- rectly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por11111111 pbc register ht68f40/ht68f50/ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por11111111 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 71 october 24, 2011 pcc register ht68f30/ht68f40/ht68f50/ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por11111111 pdc register ht68f40/ht68f50/ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por11111111 pec register ht68f40/ht68f50/ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por11111111 pfc register ht68f60 bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por11111111 bit 7~0 i/o port bit 7 ~ bit 0 input/output control 0: output 1: input pbc register ht68f20/ht68f30 bit76543210 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 000000 bit 7~6 unimplemented, read as 0 bit 5~0 pbc : port b bit 5 ~ bit 0 input/output control 0: output 1: input ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 72 october 24, 2011 pcc register ht68f20 bit76543210 name d3 d2 d1 d0 r/w r/w r/w r/w r/w por 0000 bit 7~4 unimplemented, read as 0 bit 3~0 pcc : port c bit 3 ~ bit 0 input/output control 0: output 1: input pfc register ht68f40/ht68f50 bit76543210 name d1 d0 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 pfc : port f bit 1 ~ bit 0 input/output control 0: output 1: input pgc register ht68f60 bit76543210 name d1 d0 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 pgc : port g bit 1 ~ bit 0 input/output control 0: output 1: input ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 73 october 24, 2011 pin-remapping functions the flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. the way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. additionally there are a series of prm0, prm1 and prm2 registers to establish certain pin functions. pin-remapping registers the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. some de - vices include prm0, prm1 or prm2 registers which can select the functions of certain pins. pin-remapping register list ht68f30 register name bit 76543210 prm0 pcprm simps0 pckps ht68f40 register name bit 76543210 prm0 c1xps0 c0xps0 pdprm simps1 simps0 pckps prm1 tck2ps tck1ps tck0ps int1ps1 int1ps0 int0ps1 int0ps0 prm2 tp21ps tp20ps tp1b2ps tp1aps tp01ps tp00ps ht68f50 register name bit 76543210 prm0 c1xps0 c0xps0 pdprm simps1 simps0 pckps prm1 tck2ps tck1ps tck0ps int1ps1 int1ps0 int0ps1 int0ps0 prm2 tp31ps tp30ps tp21ps tp20ps tp1b2ps tp1aps tp01ps tp00ps ht68f60 register name bit 76543210 prm0 c1xps1 c1xps0 c0xps1 c0xps0 pdprm simps1 simps0 pckps prm1 tck2ps tck1ps tck0ps int2ps1 int1ps1 int1ps0 int0ps1 int0ps0 prm2 tp31ps tp30ps tp21ps tp20ps tp1b2ps tp1aps tp01ps tp00ps ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 74 october 24, 2011 prm0 register ht68f30 bit76543210 name pcprm simps0 pckps r/w r/w r/w r/w por 000 bit 7~3 unimplemented, read as 0 bit 2 pcprm : pc1~pc0 pin-shared function pin remapping control 0: no change 1: tp1b_0 on pc0 change to pa6, tp1b_1 on pc1 change to pa7 if simps0=1 bit 1 simps0 : sim pin remapping control 0: sdo on pa5; sdi/sda on pa6; sck/scl on pa7; scs on pb5 1: sdo on pc1; sdi/sda on pc0; sck/scl on pc7; scs on pc6 bit 0 pckps : pck and pint pin remapping control 0: pck on pc2; pint on pc3 1: pck on pc5; pint on pc4 prm0 register ht68f40/ht68f50 bit76543210 name c1xps0 c0xps0 pdprm simps1 simps0 pckps r/w r/w r/w r/w r/w r/w r/w por 0 00000 bit 7 unimplemented, read as 0 bit 6 c1xps0 : c1x pin remapping control 0: c1x on pa5 1: c1x on pf1 bit 5 unimplemented, read as 0 bit 4 c0xps0 : c0x pin remapping control 0: c0x on pa0 1: c0x on pf0 bit 3 pdprm : pd3~pd0 pin-shared function pin remapping control 0: no change 1: tck2 on pd0 change to pb6, tp2_0 on pd1 change to pb7, tck0 on pd2 change to pd6, tck1 on pd3 change to pd7 if simps1, simps0=01 bit 2~1 simps1, simps0 : sim pin remapping control 00: sdo on pa5; sdi/sda on pa6; sck/scl on pa7; scs on pb5 01: sdo on pd3; sdi/sda on pd2; sck/scl on pd1; scs on pd0 10: sdo on pb6; sdi/sda on pb7; sck/scl on pd6; scs on pd7 11: undefined bit 0 pckps : pck and pint pin remapping control 0: pck on pc2; pint on pc3 1: pck on pc5; pint on pc4 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 75 october 24, 2011 prm0 register ht68f60 bit76543210 name c1xps1 c1xps0 c0xps1 c0xps0 pdprm simps1 simps0 pckps r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 c1xps1, c1xps0 : c1x pin remapping control 00: c1x on pa5 01: c1x on pf1 10: c1x on pg1 11: undefined bit 5~4 c0xps1, c0xps0 : c0x pin remapping control 00: c0x on pa0 01: c0x on pf0 10: c0x on pg0 11: undefined bit 3 pdprm : pd3~pd0 pin-shared function pin remapping control 0: no change 1: tck2 on pd0 change to pb6, tp2_0 on pd1 change to pb7, tck0 on pd2 change to pd6, tck1 on pd3 change to pd7 if simps1, simps0=01 or 11 bit 2~1 simps1, simps0 : sim pin remapping control 00: sdo on pa5; sdi/sda on pa6; sck/scl on pa7; scs on pb5 01: sdo on pd3; sdi/sda on pd2; sck/scl on pd1; scs on pd0 10: sdo on pb6; sdi/sda on pb7; sck/scl on pd6; scs on pd7 11: sdo on pd1; sdi/sda on pd2; sck/scl on pd3; scs on pd0 bit 0 pckps : pck and pint pin remapping control 0: pck on pc2; pint on pc3 1: pck on pc5; pint on pc4 prm1 register ht68f40/ht68f50 bit76543210 name tck2ps tck1ps tck0ps int1ps1 int1ps0 int0ps1 int0ps0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0000 bit 7 tck2ps : tck2 pin remapping control 0: tck2 on pc2 1: tck2 on pd0 bit 6 tck1ps : tck1 pin remapping control 0: tck1 on pa4 1: tck1 on pd3 bit 5 tck0ps : tck0 pin remapping control 0: tck0 on pa2 1: tck0 on pd2 bit 4 unimplemented, read as 0 bit 3~2 int1ps1, int1ps0 : int1 pin remapping control 00: int1 on pa4 01: int1 on pc5 10: undefined 11: int1 on pe7 bit 1~0 int0ps1, int0ps0 : int0 pin remapping control 00: int0 on pa3 01: int0 on pc4 10: undefined 11: int0 on pe6 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 76 october 24, 2011 prm1 register ht68f60 bit76543210 name tck2ps tck1ps tck0ps int2ps int1ps1 int1ps0 int0ps1 int0ps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 tck2ps : tck2 pin remapping control 0: tck2 on pc2 1: tck2 on pd0 bit 6 tck1ps : tck1 pin remapping control 0: tck1 on pa4 1: tck1 on pd3 bit 5 tck0ps : tck0 pin remapping control 0: tck0 on pa2 1: tck0 on pd2 bit 4 int2ps : int2 pin remapping control 0: int2 on pc4 1: int2 on pe2 bit 3~2 int1ps1, int1ps0 : int1 pin remapping control 00: int1 on pa4 01: int1 on pc5 10: int1 on pe1 11: int1 on pe7 bit 1~0 int0ps1, int0ps0 : int0 pin remapping control 00: int0 on pa3 01: int0 on pc4 10: int0 on pe0 11: int0 on pe6 prm2 register ht68f40 bit76543210 name tp21ps tp20ps tp1b2ps tp1aps tp01ps tp00ps r/w r/w r/w r/w r/w r/w r/w por 000000 bit 7~6 unimplemented, read as 0 bit 5 tp21ps : tp2_1 pin remapping control 0: tp2_1 on pc4 1: tp2_1 on pd4 bit 4 tp20ps : tp2_0 pin remapping control 0: tp2_0 on pc3 1: tp2_0 on pd1 bit 3 tp1b2ps : tp1b_2 pin remapping control 0: tp1b_2 on pc5 1: tp1b_2 on pe4 bit 2 tp1aps : tp1a pin remapping control 0: tp1a on pa1 1: tp1a on pc7 bit 1 tp01ps : tp0_1 pin remapping control 0: tp0_1 on pc5 1: tp0_1 on pd5 bit 0 tp00ps : tp0_0 pin remapping control 0: tp0_0 on pa0 1: tp0_0 on pc6 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 77 october 24, 2011 prm2 register ht68f50/ht68f60 bit76543210 name tp31ps tp30ps tp21ps tp20ps tp1b2ps tp1aps tp01ps tp00ps r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 tp31ps : tp3_1 pin remapping control 0: tp3_1 on pd0 1: tp3_1 on pe3 bit 6 tp30ps : tp3_0 pin remapping control 0: tp3_0 on pd3 1: tp3_0 on pe5 bit 5 tp21ps : tp2_1 pin remapping control 0: tp2_1 on pc4 1: tp2_1 on pd4 bit 4 tp20ps : tp2_0 pin remapping control 0: tp2_0 on pc3 1: tp2_0 on pd1 bit 3 tp1b2ps : tp1b_2 pin remapping control 0: tp1b_2 on pc5 1: tp1b_2 on pe4 bit 2 tp1aps : tp1a pin remapping control 0: tp1a on pa1 1: tp1a on pc7 bit 1 tp01ps : tp0_1 pin remapping control 0: tp0_1 on pc5 1: tp0_1 on pd5 bit 0 tp00ps : tp0_0 pin remapping control 0: tp0_0 on pa0 1: tp0_0 on pc6 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 78 october 24, 2011 i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. programming considerations within the user program, one of the first things to con - sider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, pac~pgc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa~pg, are first programmed. se - lecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write opera - tion takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. > 6 1 : . @ : . @ ! $ g ? g ? 9 9 : $ # ! $ : $ 9 * & g g 5 " : . 5 @ 5 @ / $ # $ generic input/output structure ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 79 october 24, 2011 timer modules tm one of the most fundamental functions in any microcontroller device is the ability to control and mea - sure time. to implement time related functions each de - vice includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, in - put capture, compare match output and single pulse output as well as being the functional unit for the gener - ation of pwm signals. each of the tms has either two or three individual interrupts. the addition of input and out - put pins for each tm ensures that users are provided with timing units with a wide and flexible range of fea - tures. the common features of the different tm types are de - scribed here with more detailed information provided in the individual compact, standard and enhanced tm sections. introduction the devices contain from two to four tms depending upon which device is selected with each tm having a reference name of tm0, tm1, tm2 and tm3. each indi - vidual tm can be categorised as a certain type, namely compact type tm, standard type tm or enhanced type tm. although similar in nature, the different tm types vary in their feature complexity. the common fea - tures to all of the compact, standard and enhanced tms will be described in this section, the detailed opera - tion regarding each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. function ctm stm etm timer/counter i/p capture compare match output pwm channels 1 1 2 single pulse output 12 pwm alignment edge edge edge & centre pwm adjustment period & duty duty or period duty or period duty or period tm function summary each device in the series contains a specific number of either compact type, standard type and enhanced type tm units which are shown in the table together with their individual reference name, tm0~tm3. device tm0 tm1 tm2 tm3 ht68f20 10-bit ctm 10-bit stm ht68f30 10-bit ctm 10-bit etm ht68f40 10-bit ctm 10-bit etm 16-bit stm ht68f50 10-bit ctm 10-bit etm 16-bit stm 10-bit ctm ht68f60 10-bit ctm 10-bit etm 16-bit stm 10-bit ctm tm name/type reference ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 80 october 24, 2011 tm operation the three different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm oper - ates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input, in effect dis - connecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two in- ternal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm out - put pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is es - sentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this ex - ternal tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have one or more output pins with the la - bel tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other func - tion, the tm output function must first be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of out- put pins for each tm type and device is different, the de- tails are provided in the accompanying table. all tm output pin names have a _n suffix. pin names that include a _1 or _2 suffix indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device ctm stm etm registers ht68f20 tp0_0 tp1_0, tp1_1 tmpc0 ht68f30 tp0_0, tp0_1 tp1a, tp1b_0, tp1b_1 tmpc0 ht68f40 tp0_0, tp0_1 tp2_0, tp2_1 tp1a, tp1b_0, tp1b_1, tp1b_2 tmpc0, tmpc1 ht68f50 tp0_0, tp0_1 tp3_0, tp3_1 tp2_0, tp2_1 tp1a, tp1b_0, tp1b_1, tp1b_2 tmpc0, tmpc1 ht68f60 tp0_0, tp0_1 tp3_0, tp3_1 tp2_0, tp2_1 tp1a, tp1b_0, tp1b_1, tp1b_2 tmpc0, tmpc1 tm output pins ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 81 october 24, 2011 tm input/output pin control registers selecting to have a tm input/output or whether to retain its other shared function, is implemented using one or two reg - isters, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corre - sponding pin as a tm input/output, if reset to zero the pin will retain its original other function. registers device bit 76543210 tmpc0 ht68f20 t1cp1 t1cp0 t0cp0 tmpc0 ht68f30 t1acp0 t1bcp1 t1bcp0 t0cp1 t0cp0 tmpc0 ht68f40 ht68f50 ht68f60 t1acp0 t1bcp2 t1bcp1 t1bcp0 t0cp1 t0cp0 tmpc1 ht68f40 t2cp1 t2cp0 tmpc1 ht68f50 ht68f60 t3cp1 t3cp0 t2cp1 t2cp0 tm input/output pin control registers list ht68f20 tm function pin control block diagram note: the i/o register data bits shown are used for tm output inversion control. in the capture input mode, the tm pin control register must never enable more than one tm input. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 82 october 24, 2011 ht68f30 tm function pin control block diagram note: the i/o register data bits shown are used for tm output inversion control. in the capture input mode, the tm pin control register must never enable more than one tm input. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 83 october 24, 2011 ht68f40 tm0 & tm2 function pin control block diagram note: the i/o register data bits shown are used for tm output inversion control. in the capture input mode, the tm pin control register must never enable more than one tm input. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 84 october 24, 2011 ht68f40 tm1 function pin control block diagram note: the i/o register data bits shown are used for tm output inversion control. in the capture input mode, the tm pin control register must never enable more than one tm input. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 85 october 24, 2011 ht68f50 and ht68f60 tm0, tm2, tm3 function pin control block diagram note: the i/o register data bits shown are used for tm output inversion control. in the capture input mode, the tm pin control register must never enable more than one tm input. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 86 october 24, 2011 ht68f50 and ht68f60 tm1 function pin control block diagram note: the i/o register data bits shown are used for tm output inversion control. in the capture input mode, the tm pin control register must never enable more than one tm input. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 87 october 24, 2011 tmpc0 register ht68f20 bit76543210 name t1cp1 t1cp0 t0cp0 r/w r/w r/w r/w por 01 1 bit 7, 6 unimplemented, read as 0 bit 5 t1cp1 : tp1_1 pin control 0: disable 1: enable bit 4 t1cp0 : tp1_0 pin control 0: disable 1: enable bit 3~1 unimplemented, read as 0 bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable ht68f30 bit76543210 name t1acp0 t1bcp1 t1bcp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w por 1 01 01 bit 7 t1acp0 : tp1a pin control 0: disable 1: enable bit 6 unimplemented, read as 0 bit 5 t1bcp1 : tp1b_1 pin control 0: disable 1: enable bit 4 t1bcp0 : tp1b_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as 0 bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 88 october 24, 2011 ht68f40/ht68f50/ht68f60 bit76543210 name t1acp0 t1bcp2 t1bcp1 t1bcp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w por1001 01 bit 7 t1acp0 : tp1a pin control 0: disable 1: enable bit 6 t1bcp2 : tp1b_2 pin control 0: disable 1: enable bit 5 t1bcp1 : tp1b_1 pin control 0: disable 1: enable bit 4 t1bcp0 : tp1b_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as 0 bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable tmpc1 register ht68f40 bit76543210 name t2cp1 t2cp0 r/w r/w r/w por 01 bit 7~2 unimplemented, read as 0 bit 1 t2cp1 : tp2_1 pin control 0: disable 1: enable bit 0 t2cp0 : tp2_0 pin control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 89 october 24, 2011 ht68f50/ht68f60 bit76543210 name t3cp1 t3cp0 t2cp1 t2cp0 r/w r/w r/w r/w r/w por 01 01 bit 7~6 unimplemented, read as 0 bit 5 t3cp1 : tp3_1 pin control 0: disable 1: enable bit 4 t3cp0 : tp3_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as 0 bit 1 t2cp1 : tp2_1 pin control 0: disable 1: enable bit 0 t2cp0 : tp2_0 pin control 0: disable 1: enable programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, being either 10-bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrb registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way described above, it is recommended to use the ?mov? instruction to ac - cess the ccra and ccrb low byte registers, named tmxal and tmxbl, using the following access procedures. ac - cessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values. the following steps show the read and write procedures: writing data to ccrb or ccra step 1. write data to low byte tmxal or tmxbl - note that here data is only written to the 8-bit buffer. step 2. write data to high byte tmxah or tmxbh - here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. data bus 8-bit buffer tmxdh tmxdl tmxbh tmxbl tmxah tmxal tm counter register (read only) tm ccra register (read/write) tm ccrb register (read/write) ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 90 october 24, 2011 reading data from the counter registers and ccrb or ccra step 1. read data from the high byte tmxdh, tmxah or tmxbh - here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. step 2. read data from the low byte tmxdl, tmxal or tmxbl - this step reads data from the 8-bit buffer. compact type tm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one or two external output pins. these two external output pins can be the same sig - nal or the inverse signal. ctm name tm no. tm input pin tm output pin ht68f20 10-bit ctm 0 tck0 tp0_0 ht68f30 10-bit ctm 0 tck0 tp0_0, tp0_1 ht68f40 10-bit ctm 0 tck0 tp0_0, tp0_1 ht68f50 10-bit ctm 0, 3 tck0, tck3 tp0_0, tp0_1; tp3_0, tp3_1 ht68f60 10-bit ctm 0, 3 tck0, tck3 tp0_0, tp0_1; tp3_0, tp3_1 compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by chang- ing the tnon bit from low to high. the counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected us- ing relevant internal registers. ! " # ! " # $ % & ' ( $ ' ) * ' ! * ' ! + * ' * ' $ ' ) " , " , + - + + . / 0 / . / 0 / . 1 2 . 1 2 . 3 4 5 compact type tm block diagram ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 91 october 24, 2011 compact type tm register description overall operation of the compact tm is controlled using six registers. a read only register pair exists to store the inter - nal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmnc0 tnpau tnck2 tnck1 tnck0 tnon tnrp2 tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d6 d5 d4 d3 d2 d1 d0 tmndh d9 d8 tmnal d7 d6 d5 d4 d3 d2 d1 d0 tmnah d9 d8 compact tm register list (n=0 or 3) tmndl register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr por00000000 bit 7~0 tmndl : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit76543210 name d9 d8 r/w rr por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tmndh : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tmnal : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 92 october 24, 2011 tmnah register bit76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tmnah : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8 tmnc0 register bit76543210 name tnpau tnck2 tnck1 tnck0 tnon tnrp2 tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 tnpau : tmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tm0 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: underined 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specified by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0 : tmn ccrp 3-bit register, compared with the tm0 counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 93 october 24, 2011 these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter's highest three bits. the result of this comparison can be selected to clear the internal counter if the tncclr bit is set to zero. setting the tncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tmnc1 register bit76543210 name tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: undefined 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefined timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the tnio1 and tnio0 bits only after the tmn has been switched off. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running bit 3 tnoc : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 94 october 24, 2011 this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bit is used to select the method which clears the counter. remember that the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode. compact type tm operating modes the compact type tm can operate in one of three oper- ating modes, compare match output mode, pwm mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter over - flow, a compare match from comparator a and a com - pare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overflow. here both tnaf and tnpf interrupt request flags for the compara - tor a and comparator p respectively, will both be gener - ated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf inter - rupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt re - quest flag will be generated. if the ccra bits are all zero, the counter will overflow when its reaches its maxi - mum 10-bit, 3ff hex, value, however here the tnaf in - terrupt request flag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when an tnaf interrupt request flag is generated after a com- pare match occurs from comparator a. the tnpf inter- rupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same in - terrupt flags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the com - pare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 95 october 24, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high compare match output mode -- tncclr = 0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 96 october 24, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change compare match output mode -- tncclr = 1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf flag is not generated when tncclr=1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 97 october 24, 2011 pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm func - tion within the tm is useful for applications which require functions such as motor control, heating control, illumi - nation control etc. by providing a signal of fixed fre - quency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with vary - ing equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polar - ity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fixed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0; tnm [1:0] = 10 pwm duty cycle set by ccra pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccrp tm o/p pin (tnoc=0) pwm mode -- tndpx = 0 note: 1. here tndpx=0 -- counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 98 october 24, 2011 counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1; tnm [1:0] = 10 pwmdutycycle set by ccrp pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccra tm o/p pin (tnoc=0) pwm mode -- tndpx = 1 note: 1. here tndp x=1-- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation ctm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra =128, the ctm pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defined by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cy - cle is defined by the ccrp register value. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 99 october 24, 2011 standard type tm - stm the standard type tm contains five operating modes, which are compare match output, timer/event counter, cap - ture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external in - put pin and can drive one or two external output pins. ctm name tm no. tm input pin tm output pin ht68f20 10-bit stm 1 tck1 tp1_0, tp1_1 ht68f30 ht68f40 16-bit stm 2 tck2 tp2_0, tp2_1 ht68f50 16-bit stm 2 tck2 tp2_0, tp2_1 ht68f60 16-bit stm 2 tck2 tp2_0, tp2_1 ! " # ! " # $ % & ' ( $ ' ) ' 6 $ ' 6 * ' ! 2 * ' ! + 2 * ' * ' $ ' ) ' $ ' 7 5 8 , " , " , + - + + . / 0 / . / 0 / . 1 2 . 1 2 . 3 4 5 standard type tm block diagram standard tm operation there are two sizes of standard tms, one is 10-bits wide and the other is 16-bits wide. at the core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, com - parator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the ccra is the ten or sixteen bits and therefore compares all counter bits. the only way of changing the value of the 10 or 16-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. when these conditions occur, a tm inter - rupt signal will also usually be generated. the standard type tm can operate in a number of different opera - tional modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using rele - vant internal registers. standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three or eight ccrp bits. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 100 october 24, 2011 name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 tm1c1 t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr tm1dl d7 d6 d5 d4 d3 d2 d1 d0 tm1dh d9 d8 tm1al d7 d6 d5 d4 d3 d2 d1 d0 tm1ah d9 d8 10-bit standard tm register list (for ht68f20) name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm2c0 t2pau t2ck2 t2ck1 t2ck0 t2on tm2c1 t2m1 t2m0 t2io1 t2io0 t2oc t2pol t2dpx t2cclr tm2dl d7 d6 d5 d4 d3 d2 d1 d0 tm2dh d15 d14 d13 d12 d11 d10 d9 d8 tm2al d7 d6 d5 d4 d3 d2 d1 d0 tm2ah d15 d14 d13 d12 d11 d10 d9 d8 tm2rp d7 d6 d5 d4 d3 d2 d1 d0 16-bit standard tm register list (for ht68f40/ht68f50/ht68f60) 10-bit standard tm register list - ht68f20 tm1c0 register - 10-bit stm bit76543210 name t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefined 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 101 october 24, 2011 bit 3 t1on : tm1 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specified by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tm1 ccrp 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter's highest three bits. the result of this comparison can be selected to clear the internal counter if the t1cclr bit is set to zero. setting the t1cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tm1c1 register - 10-bit stm bit76543210 name t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 t1m1~t1m0 : select tm1 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1m1 and t1m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1io1~t1io0 : select tp1_0, tp1_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1_0, tp1_1 01: input capture at falling edge of tp1_0, tp1_1 10: input capture at falling/rising edge of tp1_0, tp1_1 11: input capture disabled timer/counter mode: unused ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 102 october 24, 2011 these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1oc bit in the tm1c1 register. note that the output level requested by the t1io1 and t1io0 bits must be different from the initial value setup using the t1oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t1io1 and t1io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1io1 and t1io0 bits are changed when the tm is running bit 3 t1oc : tp1_0, tp1_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1pol : tp1_0, tp1_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1_0 or tp1_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1dpx : tm1 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparatror p match 1: tm1 comparatror a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 103 october 24, 2011 tm1dl register - 10-bit stm bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr por00000000 bit 7~0 tm1dl : tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm1dh register - 10-bit stm bit76543210 name d9 d8 r/w rr por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm1dh : tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 tm1al register - 10-bit stm bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tm1al : tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 tm1ah register - 10-bit stm bit76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm1ah : tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 104 october 24, 2011 16-bit standard tm register list - ht68f40/ht68f50/ht68f60 tm2c0 register - 16-bit stm bit76543210 name t2pau t2ck2 t2ck1 t2ck0 t2on r/w r/w r/w r/w r/w r/w por00000 bit 7 t2pau : tm2 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t2ck2, t2ck1, t2ck0 : select tm2 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefined 110: tck2 rising edge clock 111: tck2 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t2on : tm2 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specified by the t2oc bit, when the t2on bit changes from low to high. bit 2~0 unimplemented, read as 0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 105 october 24, 2011 tm2c1 register - 16-bit stm bit76543210 name t2m1 t2m0 t2io1 t2io0 t2oc t2pol t2dpx t2cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 t2m1~t2m0 : select tm2 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t2m1 and t2m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t2io1~t2io0 : select tp2_0, tp2_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/ single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp2_0, tp2_1 01: input capture at falling edge of tp2_0, tp2_1 10: input capture at falling/rising edge of tp2_0, tp2_1 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t2oc bit in the tm2c1 register. note that the output level requested by the t2io1 and t2io0 bits must be different from the initial value setup using the t2oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t2on bit from low to high. in the pwm mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t2io1 and t2io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t2io1 and t2io0 bits are changed when the tm is running bit 3 t2oc : tp2_0, tp2_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 106 october 24, 2011 this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2pol : tp2_0, tp2_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp2_0 or tp2_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t2dpx : tm2 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t2cclr : select tm2 counter clear condition 0: tm2 comparator p match 1: tm2 comparator a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t2cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode. tm2dl register - 16-bit stm bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr por00000000 bit 7~0 tm2dl : tm2 counter low byte register bit 7~bit 0 tm2 16-bit counter bit 7~bit 0 tm2dh register - 16-bit stm bit76543210 name d15 d14 d13 d12 d11 d10 d9 d8 r/wrrrrrrrr por00000000 bit 7~0 tm2dh : tm2 counter high byte register bit 7~bit 0 tm2 16-bit counter bit 15~bit 8 tm2al register - 16-bit stm bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tm2al : tm2 ccra low byte register bit 7~bit 0 tm2 16-bit ccra bit 7~bit 0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 107 october 24, 2011 tm2ah register - 16-bit stm bit76543210 name d15 d14 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tm2ah : tm2 ccra high byte register bit 7~bit 0 tm2 16-bit ccra bit 15~bit 8 tm2rp register - 16-bit stm bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tm2rp : tm2 ccrp register bit 7 ~ bit 0 tm2 ccrp 8-bit register, compared with the tm2 counter bit 15 ~ bit 8. comparator p match period 0: 65536 tm2 clocks 1~255: 256 x (1~255) tm2 clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counter's highest eight bits. the result of this comparison can be selected to clear the internal counter if the t2cclr bit is set to zero. setting the t2cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. standard type tm operating modes the standard type tm can operate in one of five oper- ating modes, compare match output mode, pwm out- put mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter over - flow, a compare match from comparator a and a com - pare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from compara - tor p, the other is when the ccrp bits are all zero which allows the counter to overflow. here both tnaf and tnpf interrupt request flags for comparator a and com - parator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf inter- rupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt re- quest flag will be generated. in the compare match out- put mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf interrupt request flag is generated after a com - pare match occurs from comparator a. the tnpf inter - rupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 108 october 24, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high compare match output mode -- tncclr = 0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 109 october 24, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change compare match output mode -- tncclr = 1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf flag is not generated when tncclr=1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 110 october 24, 2011 timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same in - terrupt flags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the com - pare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applica - tions which require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be gen - erated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm wave - form, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 regis - ter. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polar - ity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fixed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. 10-bit stm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra =128, the stm pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defined by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit stm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cy - cle is defined by the ccrp register value. 16-bit stm, pwm mode, edge-aligned mode, tndpx=0 ccrp 1~255 0 period ccrp 256 65536 duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 2 and ccra =128, the stm pwm output frequency = (f sys /4)/(2 256) = f sys /2048 = 7.8125 khz, duty = 128 / (2 256) = 25%. if the duty value defined by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 111 october 24, 2011 counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0; tnm [1:0] = 10 pwm duty cycle set by ccra pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccrp tm o/p pin (tnoc=0) pwm mode -- tndpx = 0 note: 1. here tndpx=0 -- counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation 16-bit stm, pwm mode, edge-aligned mode, tndpx=1 ccrp 1~255 0 period ccra duty ccrp 256 65536 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cy - cle is defined by the (ccrp x 256) except when the ccrp value is equal to 0. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 112 october 24, 2011 counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1; tnm [1:0] = 10 pwmdutycycle set by ccrp pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccra tm o/p pin (tnoc=0) pwm mode -- tndpx = 1 note: 1. here tndpx=1 -- counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no influence on pwm operation ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 113 october 24, 2011 single pulse mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the tnon bit, which can be imple - mented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse out - put. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trail - ing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from com - parator a. 5 8 7 5 8 % ' / 9 ! ! 5 / 7 : % : 3 % ' / 9 ! ! 5 : % : " # ! + 3 9 5 # ; < + + 8 7 5 8 " single pulse generation counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter stopped by ccra pause resume counter stops by software counter reset when tnon returns high tnm [1:0] = 10 ; tnio [1:0] = 11 pulse width set by ccra output inverts when tnpol = 1 no ccrp interrupts generated tm o/p pin (tnoc=0) tckn pin software trigger cleared by ccra match tckn pin trigger auto. set by tckn pin software trigger software clear software trigger software trigger single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high. 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 114 october 24, 2011 however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm inter - rupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode. capture input mode to select this mode bits tnm1 and tnm0 in the tmnc1 register should be set to 01 respectively. this mode en - ables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpn_0 or tpn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register. the counter is started when the tnon bit changes from low to high which is ini - tiated using the application program. when the required edge transition appears on the tpn_0 or tpn_1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tpn_0 or tpn_1 pin the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm inter - rupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a use - ful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn_0 or tpn_1 pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irre - spective of what happens on the tpn_0 or tpn_1 pin, however it must be noted that the counter will continue to run. as the tpn_0 or tpn_1 pin is pin shared with other func - tions, care must be taken if the tm is in the input cap - ture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an in - put capture operation to be executed. the tncclr and tndpx bits are not used in this mode. counter value yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value time counter cleared by ccrp pause resume counter reset tnm [1:0] = 01 tm capture pin tpn_x xx counter stop tnio [1:0] value xx yy xx yy active edge active edge active edge 00 rising edge 01 fallin g edge 10 both edges 11 disable capture capture input mode note: 1. tnm [1:0] = 01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function -- tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 115 october 24, 2011 enhanced type tm - etm the enhanced type tm contains five operating modes, which are compare match output, timer/event counter, cap - ture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external in - put pin and can drive three or four external output pins. ctm name tm no. tm input pin tm output pin ht68f20 ht68f30 10-bit etm 1 tck1 tp1a; tp1b_0, tp1b_1 ht68f40 10-bit etm 1 tck1 tp1a, tp1b_0, tp1b_1, tp1b_2 ht68f50 10-bit etm 1 tck1 tp1a, tp1b_0, tp1b_1, tp1b_2 ht68f60 10-bit etm 1 tck1 tp1a, tp1b_0, tp1b_1, tp1b_2 ! " # ! " # $ % & ' ( $ ' ) * ' ! * ' ! + * ' & = ' $ ' ) 7 5 8 , " , " , + - + + . / 0 / . / 0 / . 1 2 . 1 2 . 3 4 5 " , " , + - + + ! " # * ' ! 7 5 8 , * * * enhanced type tm block diagram enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. there are three internal comparators with the names, comparator a, comparator b and com - parator p. these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore com - pared with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 116 october 24, 2011 enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 tm1c1 t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr tm1c2 t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 tm1dl d7 d6 d5 d4 d3 d2 d1 d0 tm1dh d9 d8 tm1al d7 d6 d5 d4 d3 d2 d1 d0 tm1ah d9 d8 tm1bl d7 d6 d5 d4 d3 d2 d1 d0 tm1bh d9 d8 10-bit enhanced tm register list (if etm is tm1) 10-bit enhanced tm register list - ht68f30/ht68f40/ht68f50/ht68f60 tm1c0 register - 10-bit etm bit76543210 name t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefined 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t1on : tm1 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 117 october 24, 2011 if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specified by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tm1 ccrp 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter s highest three bits. the result of this comparison can be selected to clear the internal counter if the t1cclr bit is set to zero. setting the t1cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tm1c1 register - 10-bit etm bit76543210 name t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por00000000 bit 7~6 t1am1~t1am0 : select tm1 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1am1 and t1am0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1~t1aio0 : select tp1a output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/ single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1a 01: input capture at falling edge of tp1a 10: input capture at falling/rising edge of tp1a 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 118 october 24, 2011 occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register. note that the output level requested by the t1aio1 and t1aio0 bits must be different from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t1aio1 and t1aio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1aio1 and t1aio0 bits are changed when the tm is running bit 3 t1aoc : tp1a output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol : tp1a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1cdn : tm1 counter count up or down flag 0: count up 1: count down bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bit is used to select the method which clears the counter. remember that the enhanced tm contains three comparators, ccomparator a, comparator b and comparator p, but only comparator a or comparator pan be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the single pulse or input capture mode. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 119 october 24, 2011 tm1c2 register - 10-bit etm bit76543210 name t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 r/w r/w r/w r/w r/w r/w r/w r r/w por00000000 bit 7~6 t1bm1~t1bm0 : select tm1 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1bm1 and t1bm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1bio1~t1bio0 : select tp1b_0, tp1b_1, tp1b_2 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1b_0, tp1b_1, tp1b_2 01: input capture at falling edge of tp1b_0, tp1b_1, tp1b_2 10: input capture at falling/rising edge of tp1b_0, tp1b_1, tp1b_2 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register. note that the output level requested by the t1bio1 and t1bio0 bits must be different from the initial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to change the values of the t1bio1 and t1bio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1bio1 and t1bio0 bits are changed when the tm is running bit 3 t1boc : tp1b_0, tp1b_1, tp1b_2 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 120 october 24, 2011 this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol : tp1b_0, tp1b_1, tb1b_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b_0, tp1b_1, tp1b_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1~0 t1pwm1~t1pwm0 : select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down tm1dl register - 10-bit etm bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/wrrrrrrrr por00000000 bit 7~0 tm1dl : tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm1dh register - 10-bit etm bit76543210 name d9 d8 r/w rr por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm1dh : tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 tm1al register - 10-bit etm bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~0 tm1al : tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 tm1ah register - 10-bit etm bit76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm1ah : tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 121 october 24, 2011 tm1bl register - 10-bit etm bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit7~0 tm1bl : tm1 ccrb low byte register bit 7~bit 0 tm1 10-bit ccrb bit 7~bit 0 tm1bh register - 10-bit etm bit76543210 name d9 d8 r/w r/w r/w por 00 bit 7~2 unimplemented, read as 0 bit 1~0 tm1bh : tm1 ccrb high byte register bit 1~bit 0 tm1 10-bit ccrb bit 9 ~ bit 8 enhanced type tm operating modes the enhanced type tm can operate in one of five operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnam1 and tnam0 bits in the tmnc1, and the tnbm1 and tnbm0 bits in the tmnc2 register. etm operating mode ccra com- pare match output mode ccra timer/coun- ter mode ccra pwm output mode ccra single pulse output mode ccra input capture mode ccrb compare match output mode ccrb timer/counter mode ccrb pwm output mode ccrb single pulse output mode ccrb input capture mode : permitted; : not permitted compare output mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1/tmnc2 registers should be all cleared to zero. in this mode once the counter is en - abled and running it can be cleared by three methods. these are a counter overflow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a com - pare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overflow. here both the tnaf and tnpf interrupt re - quest flags for comparator a and comparator p respec - tively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf inter - rupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt re - quest flag will be generated. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 122 october 24, 2011 as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf or tnbf interrupt request flag is generated af - ter a compare match occurs from comparator a or com - parator b. the tnpf interrupt request flag, generated from a compare match from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the tnaio1 and tnaio0 bits in the tmnc1 register for etm ccra, and the tnbio1 and tnbio0 bits in the tmnc2 register for etm ccrb. the tm output pin can be selected using the tnaio1, tnaio0 bits (for the tpna pin) and tnbio1, tnbio0 bits (for the tpnb_0, tpnb_1 or tpnb_2 pins) to go high, to go low or to tog - gle from its present condition when a compare match occurs from comparator a or a compare match occurs from comparator b. the initial condition of the tm out - put pin, which is setup after the tnon bit changes from low to high, is setup using the tnaoc or tnboc bit for tpna or tpnb_0, tpnb_1, tpnb_2 output pins. note that if the tnaio1,tnaio0 and tnbio1, tnbio0 bits are zero then no pin change will take place. counter value 0x3ff ccrp ccra tnon tnpau tnapol ccrp int. flag tnpf ccra int. flag tnaf tpna o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnam [1:0] = 00 output pin set to initial level low if tnaoc=0 output toggle with tnaf flag note tnaio [1:0] = 10 active high output select here tnaio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high etm ccra compare match output mode -- tncclr = 0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tpna output pin is controlled only by the tnaf flag 3. the output pin is reset to its initial state by a tnon bit rising edge ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 123 october 24, 2011 counter value 0x3ff ccrp ccrb tnon tnpau tnbpol ccrp int. flag tnpf ccrb int. flag tnbf tpnb o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnbm [1:0] = 00 output pin set to initial level low if tnboc=0 output toggle with tnbf flag note tnbio [1:0] = 10 active high output select here tnbio [1:0] = 11 toggle output select output not affected by tnbf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnbpol is high etm ccrb compare match output mode -- tncclr = 0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tpnb output pin is controlled only by the tnbf flag 3. the output pin is reset to its initial state by a tnon bit rising edge ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 124 october 24, 2011 counter value 0x3ff ccrp ccra tnon tnpau tnapol ccrp int. flag tnpf ccra int. flag tnaf tpna o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnam [1:0] = 00 output pin set to initial level low if tnaoc=0 output toggle with tnaf flag note tnaio [1:0] = 10 active high output select here tnaio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change etm ccra compare match output mode -- tncclr = 1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tpna output pin is controlled only by the tnaf flag 3. the tpna output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf flag is not generated when tncclr=1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 125 october 24, 2011 counter value 0x3ff ccrb ccra tnon tnpau tnbpol ccrb int. flag tnbf ccra int. flag tnaf tpnb o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1; tnbm [1:0] = 00 output pin set to initial level low if tnboc=0 output toggle with tnbf flag note tnbio [1:0] = 10 active high output select here tnbio [1:0] = 11 toggle output select output not affected by tnbf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnbpol is high no tnaf flag generated on ccra overflow etm ccrb compare match output mode -- tncclr = 1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tpnb output pin is controlled only by the tnbf flag 3. the tpnb output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf flag is not generated when tncclr=1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 126 october 24, 2011 timer/counter mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 register should all be set high. the timer/counter mode operates in an identi - cal way to the compare match output mode generating the same interrupt flags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to un - derstand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respec - tively and also the tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which re - quire functions such as motor control, heating control, il - lumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit is used to determine in which way the pwm period is con- trolled. with the tncclr bit set high, the pwm period can be finely controlled using the ccra registers. in this case the ccrb registers are used to set the pwm duty value (for tpnb output pins). the ccrp bits are not used and tpna output pin is not used. the pwm output can only be generated on the tpnb output pins. with the tncclr bit cleared to zero, the pwm period is set using one of the eight values of the three ccrp bits, in multi - ples of 128. now both ccra and ccrb registers can be used to setup different duty cycle values to provide dual pwm outputs on their relative tpna and tpnb pins. the tnpwm1 and tnpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is re - set to zero. with all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially, thus reduc - ing the level of simultaneous power switching currents. interrupt flags, one for each of the ccra, ccrb and ccrp, will be generated when a compare match occurs from either the comparator a, comparator b or com - parator p. the tnaoc and tnboc bits in the tmnc1 and tmnc2 register are used to select the required polarity of the pwm waveform while the two tnaio1, tnaio0 and tnbio1, tnbio0 bits pairs are used to enable the pwm output or to force the tm output pin to a fixed high or low level. the tnapol and tnbpol bit are used to reverse the polarity of the pwm output waveform. etm, pwm mode, edge-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 a duty ccra b duty ccrb if f sys = 16mhz, tm clock source select f sys /4, ccrp = 100b, ccra = 128 and ccrb = 256, the tp1a pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125khz, duty = 128/512 = 25%. the tp1b_n pwm output frequency = (f sys /4)/512=f sys /2048 = 7.8125khz, duty = 256/512 = 50%. if the duty value defined by ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. etm, pwm mode, edge-aligned mode, tncclr=1 ccra 1 2 3 ...... 511 512 ...... 1021 1022 1023 period 1 2 3 ...... 511 512 ...... 1021 1022 1023 b duty ccrb etm, pwm mode, center-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 256 512 768 1024 1280 1536 1792 2046 a duty (ccra2) 1 b duty (ccrb2) 1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 127 october 24, 2011 etm, pwm mode, center-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period 2 4 6 1022 1024 2042 2044 2046 b duty (ccrb2) 1 counter value ccrp ccra tnon tnpau tnapol ccra int. flag tnaf ccrb int. flag tnbf tpna pin (tnaoc=1) time counter cleared by ccrp pause resume stop counter restart tncclr = 0; tnam [1:0] = 10, tnbm [1:0] = 10; tnpwm [1:0] = 00 output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high ccrb ccrp int. flag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccra duty cycle set by ccrb pwm period set by ccrp duty cycle set by ccra duty cycle set by ccra pwm mode -- edge aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 3. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 128 october 24, 2011 counter value ccra tnon tnpau tnbpol ccrb int. flag tnbf time counter cleared by ccra pause resume stop counter restart tncclr = 1; tnbm [1:0] = 10; tnpwm [1:0] = 00 output pin reset to initial value output controlled by other pin-shared function output inverts when tnbpol is high ccrb ccrp int. flag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccrb pwm period set by ccra etm pwm mode -- edge aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 3. the ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 129 october 24, 2011 counter value ccrp ccra tnon tnpau tnapol ccra int. flag tnaf ccrb int. flag tnbf tpna pin (tnaoc=1) time pause resume stop counter restart tncclr = 0; tnam [1:0] = 10, tnbm [1:0] = 10; tnpwm [1:0] = 11 output pin reset to initial value output controlled by other pin-shared function output inverts when tnapol is high ccrb ccrp int. flag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccra duty cycle set by ccrb pwm period set by ccrp etm pwm mode -- centre aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 4. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 130 october 24, 2011 counter value ccra tnon tnpau tnbpol ccra int. flag tnaf ccrb int. flag tnbf time pause resume stop counter restart tncclr = 1; tnbm [1:0] = 10; tnpwm [1:0] = 11 output pin reset to initial value output controlled by other pin-shared function ccrb tpnb pin (tnboc=1) tpnb pin (tnboc=0) duty cycle set by ccrb pwm period set by ccra output inverts when tnbpol is high ccrp int. flag tnpf pwm mode -- centre aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 131 october 24, 2011 single pulse output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respec - tively and also the corresponding tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tpna output leading edge is a low to high transition of the tnon bit, which can be im - plemented using the application program. the trigger for the pulse tpnb output leading edge is a compare match from comparator b, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automat - ically change from low to high using the external tckn pin, which will in turn initiate the single pulse output of tpna. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge of tpna will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tpna and tpnb will be generated when the tnon bit is cleared to zero, which can be im - plemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge of tpna and tpnb. in this way the ccra value can be used to control the pulse width of tpna. the ccra-ccrb value can be used to control the pulse width of tpnb. a compare match from comparator a and comparator b will also generate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used. single pulse generation ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 132 october 24, 2011 counter value ccrb ccra tnon tnpau tnapol ccrb int. flag tnbf ccra int. flag tnaf tpna pin (tnaoc=1) time counter stopped by ccra pause resume counter stops by software counter reset when tnon returns high tnam [1:0] = 10, tnbm [1:0] = 10; tnaio [1:0] = 11, tnbio [1:0] = 11 pulse width set by (ccra-ccrb) output inverts when tnbpol=1 tckn pin software trigger cleared by ccra match tckn pin trigger auto. set by tckn pin software trigger software clear software trigger software trigger tnbpol tpna pin (tnaoc=0) tpnb pin (tnboc=1) tpnb pin (tnboc=0) pulse width set by ccra output inverts when tnapol=1 etm -- single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high. 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to 11 and can not be changed. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 133 october 24, 2011 capture input mode to select this mode bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 01 respectively. this mode enables external sig - nals to capture and store the present value of the inter - nal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnaio1, tnaio0 and tnbio1, tnbio0 bits in the tmnc1 and tmnc2 registers. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the present value in the counter will be latched into the ccra and ccrb registers and a tm interrupt generated. irrespective of what events occur on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overflow in - terrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnaio1, tnaio0 and tnbio1, tnbio0 bits can select the active trigger edge on the tpna and tpnb_0, tpnb_1, tpnb_2 pins to be a rising edge, falling edge or both edge types. if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are both set high, then no capture operation will take place irrespec - tive of what happens on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, however it must be noted that the counter will continue to run. as the tpna and tpnb_0, tpnb_1, tpnb_2 pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnaoc, tnboc, tnapol and tnbpol bits are not used in this mode. counter value yy ccrp tnon tnpau ccrp int. flag tnpf ccra int. flag tnaf ccra value time counter cleared by ccrp pause resume counter reset tnam [1:0] = 01 tm capture pin tpna xx counter stop tnaio [1:0] value xx yy xx yy active edge active edge active edge 00 rising edge 01 falling edge 10 both edges 11 disable capture etm ccra capture input mode note: 1. tnam [1:0] = 01 and active edge set by the tnaio [1:0] bits 2. the tm capture input pin active edge transfers he counter value to ccra 3. tncclr bit not used 4. no output function -- tnaoc and tnapol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 134 october 24, 2011 counter value yy ccrp tnon tnpau ccrp int. flag tnpf ccrb int. flag tnbf ccrb value time counter cleared by ccrp pause resume counter reset tnbm [1:0] = 01 tm capture pin tpnb_x xx counter stop tnbio [1:0] value xx yy xx yy active edge active edge active edge 00 rising edge 01 falling edge 10 both edges 11 disable capture etm ccrb capture input mode note: 1. tnbm [1:0] = 01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. tncclr bit not used 4. no output function -- tnboc and tnbpol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 135 october 24, 2011 comparators two independent analog comparators are contained within these devices. these functions offer flexibility via their register controlled features such as power-down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused. comparator operation the device contains two comparator functions which are used to compare two analog voltages and provide an output based on their difference. full control over the two internal comparators is provided via two control reg - isters, cp0c and cp1c, one assigned to each com - parator. the comparator output is recorded via a bit in their respective control register, but can also be trans - ferred out onto a shared i/o pin. additional comparator functions include, output polarity, hysteresis functions and power down control. any pull-high resistors connected to the shared com - parator input pins will be automatically disconnected when the comparator is enabled. as the comparator in - puts approach their switching level, some spurious out - put signals may be generated on the comparator output due to the slow rising or falling nature of the input sig - nals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. ideally the comparator should switch at the point where the positive and negative inputs sig - nals are at the same voltage level, however, unavoid - able input offsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value. comparator registers there are two registers for overall comparator opera - tion, one for each comparator. as corresponding bits in the two registers have identical functions, they following register table applies to both registers. comparator register name bit 76543210 cp0c c0sel c0en c0pol c0out c0os c0hyen cp1c c1sel c1en c1pol c1out c1os c1hyen comparator registers list comparator interrupt each also possesses its own interrupt function. when any one of the changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state of the c0out or c1out bit and not the output pin which gen - erates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generated interrupt flag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt flag should be first set high before entering the sleep or idle mode. programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port con - trol register is 1 ) or read as port data register value (port control register is 0 ) if the comparator function is enabled. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 136 october 24, 2011 cp0c register bit76543210 name c0sel c0en c0pol c0out c0os c0hyen r/w r/w r/w r/w r r/w r/w por10000 1 bit 7 c0sel : select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. bit 6 c0en : comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode. bit 5 c0pol : comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c0out bit will reflect the non-inverted output condition of the comparator. if the bit is high the comparator c0out bit will be inverted. bit 4 c0out : comparator output bit c0pol=0 0: c0+ < c0- 1: c0+ > c0- c0pol=1 0: c0+ > c0- 1: c0+ < c0- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c0pol bit. bit 3 c0os : output path select 0: c0x pin 1: internal use this is the comparator output path select control bit. if the bit is set to 0 and the c0sel bit is 1 the comparator output is connected to an external c0x pin. if the bit is set to 1 or the c0sel bit is 0 the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as 0 bit 0 c0hyen : hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 137 october 24, 2011 cp1c register bit76543210 name c1sel c1en c1pol c1out c1os c1hyen r/w r/w r/w r/w r r/w r/w por10000 1 bit 7 c1sel : select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high configuration options associated with the comparator shared pins will also be automatically disconnected. bit 6 c1en : comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode. bit 5 c1pol : comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c1out bit will reflect the non-inverted output condition of the comparator. if the bit is high the comparator c1out bit will be inverted. bit 4 c1out : comparator output bit c1pol=0 0: c1+ < c1- 1: c1+ > c1- c1pol=1 0: c1+ > c1- 1: c1+ < c1- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c1pol bit. bit 3 c1os : output path select 0: c1x pin 1: internal use this is the comparator output path select control bit. if the bit is set to 0 and the c1sel bit is 1 the comparator output is connected to an external c1x pin. if the bit is set to 1 or the c1sel bit is 0 the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as 0 bit 0 c1hyen : hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specified in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 138 october 24, 2011 serial interface module sim these devices contain a serial interface module, which includes both the four line spi interface or the two line i 2 c interface types, to allow an easy method of commu - nication with external peripheral hardware. having rela - tively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim in - terface function must first be selected using a configura - tion option. as both interface types share the same pins and registers, the choice of whether the spi or i2c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o are se - lected using pull-high control registers, and also if the sim function is enabled. spi interface the spi interface is often used to communicate with ex - ternal peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple commu - nication protocol simplifying the programming require- ments when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either mas- ter or slave. although the spi interface specification can control multiple slave devices from a single master, but this device provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must first be enabled by selecting the sim enable con - figuration option and setting the correct bits in the simc0 and simc2 registers. after the spi configura - tion option has been configured it can also be addi - tionally disabled or enabled using the simen bit in the simc0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations be - ing implemented by the master. the master also con - trols the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to 1 to enable scs pin function, set csen bit to 0 the scs pin will be floating state. spi master/slave connection ! " " # " $ $ % & % & % ' $ % % " ( ) * " % ! " " % % " ( ) " ( % ( + , - ( . ( ! / " " # " 0 & & % & % 0 & & spi block diagram ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 139 october 24, 2011 the spi function in this device offers the following features: full duplex synchronous data transfer both master and slave modes lsb first or msb first data transmission modes transmission complete flag rising or falling active clock edge wcol and csen bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. there are several configuration options associated with the spi interface. one of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simc0 register will have no effect. another two spi configura - tion options determine if the csen and wcol bits are to be used. spi registers there are three internal registers which control the over - all operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 76543210 simc0 sim2 sim1 sim0 pcken pckp1 pckp0 simen simd d7 d6 d5 d4 d3 d2 d1 d0 simc2 d7 d6 ckpolb ckeg mls csen wcol trf sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmis- sion or reception of data from the spi bus must be made via the simd register. simd register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w p o rxxxxxxxx x unknown ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 140 october 24, 2011 there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmission clock fre - quency. although not connected with the spi function, the simc0 register is also used to control the peripheral clock prescaler. register simc2 is used for other control functions such as lsb/msb selection, write collision flag etc. simc0 register bit76543210 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por1110000 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a floating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim configuration option must have first enabled the sim interface for this bit to be effective. if the sim is configured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be first initialised by the application program. if the sim is configured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 141 october 24, 2011 simc2 register bit76543210 name d7 d6 ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 undefined bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and placed into a floating condition. if the bit is high the scs pin will be enabled and used as a select pin. note that using the csen bit can be disabled or enabled via configuration option. bit 1 wcol : spi write collision flag 0: no collision 1: collision the wcol flag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcol bit can be disabled or enabled via configuration option. bit 0 trf : spi transmit/receive complete flag 0: data is being transferred 1: spi data transmission is completed the trf bit is the transmit/receive complete flag and is set 1 automatically when an spi data transmission is completed, but must set to 0 by the application program. it can be used to generate an interrupt. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 142 october 24, 2011 1 2 3 4 1 2 , 4 # 5 , 6 3 7 / 8 9 9 8 / 7 3 6 , 5 ' " 1 * " " ( % * 4 spi slave mode timing ckeg=0 spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simd register, transmission/reception will begin si - multaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the ap - propriate moment relative to the scs signal depending upon the configurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the rela - tionship between the slave data and scs signal for vari - ous configurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode. 1 2 3 : ; 2 , 4 0 : 0 2 3 0 2 3 : 0 2 , 1 % % % < 4 1 2 , : ; 2 , 4 1 2 3 : ; 2 3 4 1 2 , : ; 2 3 4 1 ; 2 , 4 1 ; 2 3 4 # 5 , 6 3 7 / 8 9 9 8 / 7 3 6 , 5 5 , 6 3 7 / 8 9 9 8 / 7 3 6 , 5 ' " spi master mode timing ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 143 october 24, 2011 0 2 3 ' " ' 2 3 = % ' + - " ( " - # % * = 1 $ 2 3 = 4 0 + * " - % $ $ * = 0 + 0 - " % > = % > ? ? " : ; : 0 * @ / a , b 2 , , , : , , 3 : , 3 , : , 3 3 " 3 , , @ / a , b 2 3 , 3 0 spi transfer control flowchart 1 2 3 4 1 2 , 4 # 5 , 6 3 7 / 8 9 9 8 / 7 3 6 , 5 ' " 1 ( " " c " ( ( d % " 2 3 4 0 " a $ " % > - " * : 0 2 3 * 0 2 , : % c ! & % * * " % > % e spi slave mode timing ckeg=1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 144 october 24, 2011 i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data trans - fer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this rea - son it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identified by a unique address which will be transmitted and re- ceived on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several configuration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simc0 register will have no effect. a configuration op - tion determines the debounce time of the i 2 c inter - face. this uses the system clock to in effect add a debounce time to the external clock to reduce the pos - sibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 2 or 4 system clocks. to achieve the required i 2 c data transfer speed, there exists a re - lationship between the system clock, f sys , and the i 2 c debounce time. for either the i 2 c standard or fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following ta - ble. i 2 c debounce time selection i 2 c standard mode (100khz) i 2 c fast mode (400khz) no debounce f sys > 2mhz f sys > 5mhz 2 system clock debounce f sys > 4mhz f sys > 10mhz 4 system clock debounce f sys > 8mhz f sys > 20mhz i 2 c minimum f sys frequency i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sima and one data regis - ter, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 cin - terface. ? % " - * % > * * * ' & " - ? ( ) " c % * " - % > * * & ! " - ? ( ) " c % * " - % > % " - > ( % > > ( > ( % > f ? i 2 c master slave bus connection ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 145 october 24, 2011 register name bit 76543210 simc0 sim2 sim1 sim0 pcken pckp1 pckp0 simen simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d6 d5 d4 d3 d2 d1 d0 sima iica6 iica5 iica4 iica3 iica2 iica1 iica0 d0 i 2 c registers list simc0 register bit76543210 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por1110000 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a floating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim configuration option must have first enabled the sim interface for this bit to be effective. if the sim is configured to operate as an spi interface via sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be first initialised by the application program. if the sim is configured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as 0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 146 october 24, 2011 simc1 register bit76543210 name hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r por10000001 bit 7 hcf:i 2 c bus data transfer completion flag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas:i 2 c bus address match flag 0: not address match 1: address match the hass flag is the address match flag. this flag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the flag will be low. bit 5 hbb:i 2 c bus busy flag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i 2 c busy flag. this flag will be 1 when the i 2 c bus is busy which will occur when a start signal is detected. the flag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak:i 2 c bus transmit acknowledge flag 0: slave send acknowledge flag 1: slave do not send acknowledge flag the txak bit is the transmit acknowledge flag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to 0 before further data is received. bit 2 srw :i 2 c slave read/write flag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is the i 2 c slave read/write flag. this flag determines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas flag is set high, the slave device will check the srw flag to determine whether it should be in transmit mode or receive mode. if the srw flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu:i 2 c address match wake-up control 0: disable 1: enable - must be cleared by the application program after wake-up this bit should be set to 1 to enable the i 2 c address match wake up from the sleep or idle mode. if the iamwu bit has been set before entering either the sleep or idle mode to enable the i 2 c address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. bit 0 rxak:i 2 c bus receive acknowledge flag 0: slave receive acknowledge flag 1: slave do not receive acknowledge flag the rxak flag is the receiver acknowledge flag. when the rxak flag is 0 , it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak flag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak flag is 1 . when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 147 october 24, 2011 the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmis - sion or reception of data from the spi bus must be made via the simd register. simd register bit76543210 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w porxxxxxxxx x unknown sima register bit76543210 name iica6 iica5 iica4 iica3 iica2 iica1 iica0 r/w r/w r/w r/w r/w r/w r/w r/w porxxxxxxx x unknown bit 7~1 iica6~ iica0 :i 2 c slave address iica6~ iica0 is the i 2 c slave address bit 6~ bit 0. the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~ 1 of the sima register define the device slave address. bit 0 is not defined. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefined bit this bit can be read or written by user software program. / 1 4 % > ? * * 1 ? 4 ( " " " % ? * * ( < ? ? / # - ( > " " % g & " - # % ( " " # ? * * " - # " & % & % ? ( ) " c % * * c % > ' < < < $ & " ( ( ! ? " " # " i 2 c block diagram ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 148 october 24, 2011 i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmis - sion, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all de - vices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. the first seven bits of the data will be the slave address with the first bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must first check the condition of the haas bit to determine whether the interrupt source orig - inates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must in - itialise the bus, the following are steps to achieve this: step 1 set the sim2~sim0 and simen bits in the simc0 regis - ter to 1 to enable the i 2 c bus. step 2 write the slave address of the device to the i 2 c bus ad- dress register sima. step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim inter- rupt and multi-function interrupt. i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave de - vice. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transi - tion on the sda line takes place when the scl line re - mains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out im - mediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus in - terrupt signal will be generated. the next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowl - edge bit, which is a low level, as the 9th bit. the slave device will also set the status flag haas when the ad- dresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the inter- rupt source has come from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the srw bit in the simc1 register defines whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should exam - ine this bit to determine if it is to be a transmitter or a re - ceiver. if the srw flag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw flag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an ac - knowledge signal. the acknowledge signal will inform ' % > ? * * " ? @ / a , b 2 3 3 , 0 / # 2 = + 0 " * $ ' " # ; " " " - " % % $ " * ( * c " " " / ; " " " - i 2 c bus initialisation flow chart ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 149 october 24, 2011 the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas flag is high, the addresses have matched and the slave de - vice must check the srw flag to determine if it is to be a transmitter or a receiver. if the srw flag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to 1 .ifthe srw flag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to 0. i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted af - ter the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level 0 , before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmit - ter, the slave device must first write the data to be trans - mitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a trans - mitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. 3 , 3 , , 3 ,, 3 , , 3 , 3 , 3 3 2 1 3 & 4 ? 2 % > ? * * 1 5 & 4 2 ' & 1 3 & 4 2 % > * > ( * ( ) " c % * & 1 3 & 4 2 1 g & 4 ? 2 ? 1 ? & " - : ? & " ( > 3 & 4 2 " # 1 3 & 4 ? ' ? ? " # ? % > ? * * ? ? ? ? ? ? note: * when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c communication timing diagram ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 150 october 24, 2011 < ? ? 2 3 = < 2 3 = ' 2 3 = + 0 " + 0 " ? 2 3 = + 0 " 0 " * " - " % % + - - ! * " - " % ' * " % < ' * " " % < ? - - ! * " - " % < ? i 2 c bus isr flow chart ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 151 october 24, 2011 peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simc0 register. the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can originate from either the tm0 ccrp match frequency/2 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 reg - ister is the overall on/off control, setting pcken bit to 1 enables the peripheral clock, setting pcken bit to 0 disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. if the device enters the sleep mode this will disable the peripheral clock output. simc0 register bit76543210 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por1110000 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a floating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim configuration option must have first enabled the sim interface for this bit to be effective. note that when the simen bit changes from low to high the contents of the spi control registers will be in an unknown condition and should therefore be first initialised by the application program. bit 0 unimplemented, read as 0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 152 october 24, 2011 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module requires microcontroller atten - tion, their corresponding interrupt will enforce a tempo - rary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int3 and pint pins, while the internal interrupts are gener - ated by various internal functions such as the tms, comparators, time base, lvd, eeprom and sim. interrupt registers overall interrupt control, which basically means the set - ting of request flags when certain microcontroller condi - tions occur and the setting of interrupt enable bits by the application program, is controlled by a series of regis - ters, located in the special purpose data memory, as shown in the accompanying table. the number of regis - ters depends upon the device chosen but fall into three categories. the first is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi3 registers which setup the multi-function in - terrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the nam- ing convention of these follows a specific pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for en - able/disable bit or f for request flag. function enable bit request flag notes global emi comparator cpne cpnf n=0or1 intn pin intne intnf n = 0~3 multi-function mfne mfnf n = 0~5 time base tbne tbnf n=0or1 sim sime simf lvd lve lvf eeprom dee def pint pin xpe xpf tm tnpe tnpf n = 0~3 tnae tnaf tnbe tnbf interrupt register bit naming conventions interrupt register contents ht68f20 name bit 76543210 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 mf1f mf0f cp1f mf1e mf0e cp1e intc2 mf3f tb1f tb0f mf2f mf3e tb1e tb0e mf2e mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi2 def lvf xpf simf dee lve xpe sime ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 153 october 24, 2011 ht68f30 name bit 76543210 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 mf1f mf0f cp1f mf1e mf0e cp1e intc2 mf3f tb1f tb0f mf2f mf3e tb1e tb0e mf2e mfi0 t0af t0pf t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi2 def lvf xpf simf dee lve xpe sime ht68f40 name bit 76543210 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 mf1f mf0f cp1f mf1e mf0e cp1e intc2 mf3f tb1f tb0f mf2f mf3e tb1e tb0e mf2e mfi0 t2af t2pf t0af t0pf t2ae t2pe t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi2 def lvf xpf simf dee lve xpe sime ht68f50 name bit 76543210 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 mf1f mf0f cp1f mf1e mf0e cp1e intc2 mf3f tb1f tb0f mf2f mf3e tb1e tb0e mf2e mfi0 t2af t2pf t0af t0pf t2ae t2pe t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi2 def lvf xpf simf dee lve xpe sime mfi3 t3af t3pf t3ae t3pe ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 154 october 24, 2011 ht68f60 name bit 76543210 integ int3s1 int3s0 int2s1 int2s0 int1s1 int1s0 int0s1 int0s0 intc0 int2f int1f int0f int2e int1e int0e emi intc1 mf0f cp1f cp0f int3f mf0e cp1e cp0e int3e intc2 mf3f mf2f mf1f mf3e mf2e mf1e intc3 mf5f tb1f tb0f mf4f mf5e tb1e tb0e mf4e mfi0 t2af t2pf t0af t0pf t2ae t2pe t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi2 def lvf xpf simf dee lve xpe sime mfi3 t3af t3pf t3ae t3pe integ register ht68f20/ht68f30/ht68f40/ht68f50 bit76543210 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0000 bit 7~4 unimplemented, read as 0 bit 3~2 int1s1, int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 155 october 24, 2011 ht68f60 bit76543210 name int3s1 int3s0 int2s1 int2s0 int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7~6 int3s1, int3s0 : interrupt edge control for int3 pin 00: disable 01: rising edge 10: falling edge bit 5~4 int2s1, int2s0 : interrupt edge control for int2 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 3~2 int1s1, int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges intc0 register ht68f20/ht68f30/ht68f40/ht68f50 bit76543210 name cp0f int1f int0f cp0e int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0000000 bit 7 unimplemented, read as 0 bit 6 cp0f : comparator 0 interrupt request flag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request flag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request flag 0: no request 1: interrupt request bit 3 cp0e : comparator 0 interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 156 october 24, 2011 ht68f60 bit76543210 name int2f int1f int0f int2e int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0000000 bit 7 unimplemented, read as 0 bit 6 int2f : int2 interrupt request flag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request flag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request flag 0: no request 1: interrupt request bit 3 int2e : int2 interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 157 october 24, 2011 intc1 register ht68f20/ht68f30/ht68f40/ht68f50 bit76543210 name mf1f mf0f cp1f mf1e mf0e cp1e r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 5 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 4 cp1f : comparator 1 interrupt request flag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 1 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 0 cp1e : comparator 1 interrupt control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 158 october 24, 2011 ht68f60 bit76543210 name mf0f cp1f cp0f int3f mf0e cp1e cp0e int3e r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 6 cp1f : comparator 1 interrupt request flag 0: no request 1: interrupt request bit 5 cp0f : comparator 0 interrupt request flag 0: no request 1: interrupt request bit 4 int3f : int3 interrupt request flag 0: no request 1: interrupt request bit 3 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 2 cp1e : comparator 1 interrupt control 0: disable 1: enable bit 1 cp0e : comparator 0 interrupt control 0: disable 1: enable bit 0 int3e : int3 interrupt control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 159 october 24, 2011 intc2 register ht68f20/ht68f30/ht68f40/ht68f50 bit76543210 name mf3f tb1f tb0f mf2f mf3e tb1e tb0e mf2e r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 mf3f : multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 6 tb1f : time base 1 interrupt request flag 0: no request 1: interrupt request bit 5 tb0f : time base 0 interrupt request flag 0: no request 1: interrupt request bit 4 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 3 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 2 tb1e : time base 1 interrupt control 0: disable 1: enable bit 1 tb0e : time base 0 interrupt control 0: disable 1: enable bit 0 mf2e : multi-function interrupt 2 control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 160 october 24, 2011 ht68f60 bit76543210 name mf3f mf2f mf1f mf3e mf2e mf1e r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 mf3f : multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 5 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 4 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 1 mf2e : multi-function interrupt 2 control 0: disable 1: enable bit 0 mf1e : multi-function interrupt 1 control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 161 october 24, 2011 intc3 register ht68f60 bit76543210 name mf5f tb1f tb0f mf4f mf5e tb1e tb0e mf4e r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 mf5f : multi-function interrupt 5 request flag 0: no request 1: interrupt request bit 6 tb1f : time base 1 interrupt request flag 0: no request 1: interrupt request bit 5 tb0f : time base 0 interrupt request flag 0: no request 1: interrupt request bit 4 mf4f : multi-function interrupt 4 request flag 0: no request 1: interrupt request bit 3 mf5e : multi-function interrupt 5 control 0: disable 1: enable bit 2 tb1e : time base 1 interrupt control 0: disable 1: enable bit 1 tb0e : time base 0 interrupt control 0: disable 1: enable bit 0 mf4e : multi-function interrupt 4 control 0: disable 1: enable mfi0 register ht68f20/ht68f30 bit76543210 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 00 00 bit 7~6 unimplemented, read as 0 bit 5 t0af : tm0 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 162 october 24, 2011 ht68f40/ht68f50/ht68f60 bit76543210 name t2af t2pf t0af t0pf t2ae t2pe t0ae t0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 t2af : tm2 comparator a match interrupt request flag 0: no request 1: interrupt request bit 6 t2pf : tm2 comparator p match interrupt request flag 0: no request 1: interrupt request bit 5 t0af : tm0 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 2 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register ht68f20 bit76543210 name t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 00 00 bit 7~6 unimplemented, read as 0 bit 5 t1af : tm1 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 163 october 24, 2011 ht68f30/ht68f40/ht68f50/ht68f60 bit76543210 name t1bf t1af t1pf t1be t1ae t1pe r/w r/w r/w r/w r/w r/w r/w por 000 000 bit 7 unimplemented, read as 0 bit 6 t1bf : tm1 comparator b match interrupt request flag 0: no request 1: interrupt request bit 5 t1af : tm1 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 t1be : tm1 comparator b match interrupt control 0: disable 1: enable bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable mfi2 register bit76543210 name def lvf xpf simf dee lve xpe sime r/w r/w r/w r/w r/w r/w r/w r/w r/w por00000000 bit 7 def : data eeprom interrupt request flag 0: no request 1: interrupt request bit 6 lvf : lvd interrupt request flag 0: no request 1: interrupt request bit 5 xpf : external peripheral interrupt request flag 0: no request 1: interrupt request bit 4 simf : sim interrupt request flag 0: no request 1: interrupt request bit 3 dee : data eeprom interrupt control 0: disable 1: enable bit 2 lve : lvd interrupt control 0: disable 1: enable bit 1 xpe : external peripheral interrupt control 0: disable 1: enable bit 0 sime : sim interrupt control 0: disable 1: enable ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 164 october 24, 2011 mfi3 register ht68f50/ht68f60 bit76543210 name t3af t3pf t3ae t3pe r/w r/w r/w r/w r/w por 00 00 bit 7~6 unimplemented, read as 0 bit 5 t3af : tm3 comparator a match interrupt request flag 0: no request 1: interrupt request bit 4 t3pf : tm3 comparator p match interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t3ae : tm3 comparator a match interrupt control 0: disable 1: enable bit 0 t3pe : tm3 comparator p match interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p, comparator a or comparator b match etc, the relevant interrupt request flag will be set. whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt re - quest flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be ex - ecuted, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another sec - tion of program which is known as the interrupt service routine. here is located the code to control the appropri - ate interrupt. the interrupt service routine must be ter - minated with a reti , which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their as- sociated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any fur- ther interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the re - quest flag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to al - low interrupt nesting. if the stack is full, the interrupt re - quest will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decre - mented. if immediate service is desired, the stack must be prevented from becoming full. in case of simulta - neous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request flags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occur - ring the corresponding flag should be set before the de - vice is in sleep or idle mode. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 165 october 24, 2011 04h 08h 0ch 10h 14h 18h 20h 24h 28h vector low priority high request flags enable bits master enable request flags enable bits emiautodisabledinisr interrupts contained within multi-function interrupts interrupt name interrupt name ht68f30 only mf3f m. funct. 3 mf3e xpf pint pin xpe emi 2ch lvf lvd lve def eeprom dee emi emi emi emi emi emi emi emi emi simf sim sime t1bf tm1 b t1be t1af tm1 a t1ae t1pf tm1 p t1pe t0af tm0 a t0ae t0pf tm0 p t0pe int0f int0 pin int0e int1f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e mf0f m. funct. 0 mf0e mf1f m. funct. 1 mf1e mf2f m. funct. 2 mf2e tb0f time base 0 tb0e tb1f time base 1 tb1e xxf legend request flag ? no auto reset in isr xxf request flag ? auto reset in isr xxe enable bit interrupt structure ht68f20/ht68f30 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 166 october 24, 2011 04h 0ch 14h 18h 20h 24h 28h request flags enable bits interrupts contained within multi-function interrupts interrupt name mf3f m. funct. 3 mf3e xpf pint pin xpe emi lvf lvd lve def eeprom dee emi emi emi emi emi emi emi emi emi simf sim sime t1bf tm1 b t1be t1af tm1 a t1ae t1pf tm1 p t1pe tp0af tm0 a t0ae tp0af tm0 p t0pe int0f int0 pin int0e int1 f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e mf0f m. funct. 0 mf0e mf1f m. funct. 1 mf1e mf2f m. funct. 2 mf2e tb0f time base 0 tb0e tb1f time base 1 tb1e t2af tm2 a t2ae t2pf tm2 p t2pe t3af tm3 a t3ae t3pf tm3 p t3pe ht68f50 onl y low priority high xxf legend request flag ? no auto reset in isr xxf request flag ? auto reset in isr xxe enable bit vector request flags enable bits master en ab le emiautodisabledinisr interrupt name 08h 2ch 10h interrupt structure ht68f40/ht68f50 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 167 october 24, 2011 04h 08h 14h 18h 1ch 20h 24h 34h 38h request flags enable bits emiautodisabledinisr interrupts contained within multi-function interrupts interrupt name xxf legend request flag ? no auto reset in isr xxf request flag ? auto reset in isr xxe enable bit xxf legend request flag ? no auto reset in isr xxf request flag ? auto reset in isr xxe enable bit mf3f m. funct. 3 mf3e xpf pint pin xpe emi 28h lvf lvd lve def eeprom dee emi emi emi emi emi emi emi emi emi simf sim sime t1bf tm1 b t1be t1af tm1 a t1ae t1pf tm1 p t1pe t0af tm0 a t0ae t0pf tm0 p t0pe int0 f int0 pin int0e int1f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e mf0f m. funct. 0 mf0e mf1f m. funct. 1 mf1e mf2f m. funct. 2 mf2e tb0f time base 0 tb0e tb1f time base 1 tb1e t3af tm3 a t3ae t3pf tm3 p t3pe emi emi int2f int2 pin int2 e int3f int3 pin int3 e 0ch 10h mf5f m. funct. 5 mf5e emi 3ch 30h emi mf4f m. funct. 4 mf4e t2af tm2 a t2ae t2pf tm2 p t2pe low pr ior ity high vector request flags enable bits master enable in te rrup t name interrupt structure ht68f60 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 168 october 24, 2011 external interrupt the external interrupts are controlled by signal transi - tions on the pins int0~int3. an external interrupt re - quest will take place when the external interrupt request flags, int0f~int3f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the pro - gram to branch to its respective interrupt vector ad - dress, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int3e, must first be set. additionally the correct interrupt edge type must be selected using the integ register to en - able the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external inter - rupt request flags, int0f~int3f, will be automatically reset and the emi bit will be automatically cleared to dis - able other interrupts. note that any pull-high resistor se- lections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ reg- ister can also be used to disable the external interrupt function. comparator interrupt the comparator interrupt is controlled by the two inter - nal comparators. a comparator interrupt request will take place when the comparator interrupt request flags, cp0f or cp1f, are set, a situation that will occur when the comparator output changes state. to allow the pro - gram to branch to its respective interrupt vector ad - dress, the global interrupt enable bit, emi, and comparator interrupt enable bits, cp0e and cp1e, must first be set. when the interrupt is enabled, the stack is not full and the comparator inputs generate a compara - tor output transition, a subroutine call to the comparator interrupt vector, will take place. when the interrupt is serviced, the external interrupt request flags, will be au - tomatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt within these devices there are up to six multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, sim interrupt, external peripheral in - terrupt, lvd interrupt and eeprom interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request flags, mf0f~mf5f are set. the multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request flag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, it must be noted that, although the multi-function interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the multi-function interrupts, namely the tm interrupts, sim interrupt, external peripheral in- terrupt, lvd interrupt and eeprom interrupt will not be automatically reset and must be manually reset by the application program. time base interrupts the function of the time base interrupts is to provide reg- ular time signal in the form of an internal interrupt. they are controlled by the overflow signals from their respec- tive timer functions. when these happens their respec - tive interrupt request flags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must first be set. when the interrupt is enabled, the stack is not full and the time base overflows, a subroutine call to their respective vector locations will take place. when the interrupt is ser - viced, the respective interrupt request flag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 169 october 24, 2011 the purpose of the time base interrupt is to provide an interrupt signal at fixed time periods. their clock sources origi - nate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is se - lected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section. tbc register bit76543210 name tbon tbck tb11 tb10 lxtlp tb02 tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por00110111 bit 7 tbon : tb0 and tb1 control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10 : select time base 1 time-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 lxtlp : lxt low power control 0: disable 1: enable bit 2~0 tb02~tb00 : select time base 0 time-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb + 8 / h / g 3 7 / h / 3 / 3 7 3 3 h 3 , - , # - 3 # " " # " , / h , , time base interrupt ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 170 october 24, 2011 serial interface module interrupt the serial interface module interrupt, also known as the sim interrupt, is contained within the multi-function in - terrupt. a sim interrupt request will take place when the sim interrupt request flag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, and muti-function interrupt enable bits, must first be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or re - ceived by the sim interface, a subroutine call to the re - spective multi-function interrupt vector, will take place. when the serial interface interrupt is serviced, the emi bit will be automatically cleared to disable other inter - rupts, however only the multi-function interrupt request flag will be also automatically cleared. as the simf flag will not be automatically cleared, it has to be cleared by the application program. external peripheral interrupt the external peripheral interrupt operates in a similar way to the external interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt re- quest flag, xpf, is set, which occurs when a negative edge transition appears on the pint pin. to allow the program to branch to its respective interrupt vector ad- dress, the global interrupt enable bit, emi, external pe- ripheral interrupt enable bit, xpe, and associated multi-function interrupt enable bit, must first be set. when the interrupt is enabled, the stack is not full and a negative transition appears on the external peripheral interrupt pin, a subroutine call to the respective multi-function interrupt, will take place. when the exter - nal peripheral interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, how - ever only the multi-function interrupt request flag will be also automatically cleared. as the xpf flag will not be automatically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with different functions. it must therefore be prop - erly configured to enable it to operate as an external pe - ripheral interrupt pin. eeprom interrupt the eeprom interrupt, is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def, is set, which occurs when an eeprom write or read cycle ends. to allow the program to branch to its respective interrupt vector address, the global inter - rupt enable bit, emi, eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must first be set. when the interrupt is enabled, the stack is not full and an eeprom write or read cycle ends, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom in - terrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automat - ically cleared. as the def flag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. an lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector func - tion detects a low power supply voltage. to allow the program to branch to its respective interrupt vector ad - dress, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must first be set. when the interrupt is enabled, the stack is not full and a low voltage condi - tion occurs, a subroutine call to the multi-function inter - rupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request flag will be also automat- ically cleared. as the lvf flag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and standard type tms have two inter- rupts each, while the enhanced type tm has three in- terrupts. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact and standard type tms there are two interrupt request flags tnpf and tnaf and two enable bits tnpe and tnae. for the enhanced type tm there are three interrupt re - quest flags tnpf, tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request flags are set, a situa - tion which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, re - spective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must first be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subrou - tine call to the relevant multi-function interrupt vector lo - cations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to dis - able other interrupts, however only the related mfnf flag will be automatically cleared. as the tm interrupt re - quest flags will not be automatically cleared, they have to be cleared by the application program. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 171 october 24, 2011 interrupt wake-up function each of the interrupt functions has the capability of wak - ing up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt re - quest flag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as ex - ternal edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be dis - abled then the corresponding interrupt request flag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling the relevant interrupt enable bits, a re - quested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will re - main in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request flags, mf0f~mf5f, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. inter - rupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control se - quence will be damaged once a call subroutine is exe - cuted in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request flag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are al - tered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 172 october 24, 2011 power down mode and wake-up entering the idle or sleep mode there is only one way for the device to enter the sleep or idle mode and that is to execute the halt instruc - tion in the application program. when this instruction is executed, the following will occur: the system clock will be stopped and the application program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock source and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit de - signer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be con- nected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. this also applies to de- vices which have different package types, as there may be unbonbed pins. these must either be setup as out- puts or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as out - puts. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the configuration options have enabled the lirc oscillator. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status. each pin on port a can be setup using the pawu regis - ter to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the pro- gram will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possi- ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe- cution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up func - tion of the related interrupt will be disabled. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 173 october 24, 2011 low voltage detector lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the sup - ply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be gener - ated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fixed voltages below which a low voltage condition will be detemined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a cer - tain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit76543210 name lvdo lvden vlvd2 vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 00 000 bit 7~6 unimplemented, read as 0 bit 5 lvdo : lvd output flag 0: no low voltage detect 1: low voltage detect bit lvden : low voltage detector control 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 vlvd2 ~ vlvd0 : select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.4v ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 174 october 24, 2011 lvd operation the low voltage detector function operates by compar - ing the power supply voltage, v dd , with a pre-specified voltage level stored in the lvdc register. this has a range of between 2.0v and 4.4v. when the power sup - ply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power sup - ply voltage condition. the low voltage detector func - tion is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage de - tector, a time delay t lvds should be allowed for the cir - cuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. the low voltage detector also has its own interrupt which is contained within one of the multi-function inter- rupts, providing an alternative means of low voltage de- tection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request flag will be set, causing an in- terrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage de - tector wake up function is not required then the lvf flag should be first set high before the device enters the sleep or idle mode. scom function for lcd the devices have the capability of driving external lcd panels. the common pins for lcd driving, scom0~ scom3, are pin shared with certain pin on the pc0~ pc3 or pc0 ~ pc1, pc6 ~ pc7 port. the lcd signals (com and seg) are generated using the application program. lcd operation an external lcd panel can be driven using this device by configuring the pc0~pc3 or pc0 ~ pc1, pc6 ~ pc7 pins as common pins and using other output ports lines as segment pins. the lcd driver function is controlled using the scomc register which in addition to control - ling the overall on/off function also controls the bias volt - age setup function. this enables the lcd com driver to generate the necessary v dd /2 voltage levels for lcd 1/2 bias operation. the scomen bit in the scomc register is the overall master control for the lcd driver, however this bit is used in conjunction with the comnen bits to select which port c pins are used for lcd driving. note that the port control register does not need to first setup the pins as outputs to enable the lcd driver operation. scomen comnen pin function o/p level 0 x i/o 0or1 1 0 i/o 0or1 1 1 scomn v dd /2 output control lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is imple - mented using the isel1 and isel0 bits in the scomc register. f f f f 0 f f lvd operation f , h 9 0 0 f / " # ( lcd com bias ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 175 october 24, 2011 scomc register ht68f20 bit76543210 name d7 isel1 isel0 scomen com3en com2en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 00000000 bit 7 reserved bit 0: correct level - bit must be reset to zero for correct operation 1: unpredictable operation - bit must not be set high bit 6~5 isel1, isel0 : isel1 ~ isel0: select scom typical bias current (v dd =5v) 00: 25 a 01: 50 a 10: 100 a 11: 200 a bit 4 scomen : scom module control 0: disable 1: enable bit 3 com3en : pc3 or scom3 selection 0: gpio 1: scom3 bit 2 com2en : pc2 or scom2 selection 0: gpio 1: scom2 bit 1 com1en : pc1 or scom1 selection 0: gpio 1: scom1 bit 0 com0en : pc0 or scom0 selection 0: gpio 1: scom0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 176 october 24, 2011 ht68f30/ht68f40/ht68f50/ht68f60 bit76543210 name d7 isel1 isel0 scomen com3en com2en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 00000000 bit 7 reserved bit 0: correct level - bit must be reset to zero for correct operation 1: unpredictable operation - bit must not be set high bit 6~5 isel1, isel0 : select scom typical bias current (v dd =5v) 00: 25 a 01: 50 a 10: 100 a 11: 200 a bit 4 scomen : scom module control 0: disable 1: enable bit 3 com3en : pc7 or scom3 selection 0: gpio 1: scom3 bit 2 com2en : pc6 or scom2 selection 0: gpio 1: scom2 bit 1 com1en : pc1 or scom1 selection 0: gpio 1: scom1 bit 0 com0en : pc0 or scom0 selection 0: gpio 1: scom0 configuration options configuration options refer to certain options within the mcu that are programmed into the device during the program - ming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defined for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed system oscillator selection - f h : 1. hxt 2. erc 3. hirc 2 low speed system oscillator selection - f l : 1. lxt 2. lirc 3 wdt clock selection - f s : 1. f sub 2. f sys /4 4 hirc frequency selection: 1. 4mhz 2. 8mhz 3. 12mhz note: the f sub and the f tbc clock source are lxt or lirc selection by the f l configuration option. reset pin options 5 pb0/res pin options: 1. res pin 2. i/o pin watchdog options 6 watchdog timer function: 1. enable 2. disable 7 clrwdt instructions selection: 1. 1 instructions 2. 2 instructions lvr options 8 lvr function: 1. enable 2. disable 9 lvr voltage selection: 1. 2.10v 2. 2.55v 3. 3.15v 4. 4.20v ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 177 october 24, 2011 no. options sim options 10 sim function: 1. enable 2. disable 11 spi - wcol bit: 1. enable 2. disable 12 spi - csen bit: 1. enable 2. disable 13 i 2 c debounce time selection: 1. no debounce 2. 2 system clock debounce 3. 4 system clock debounce application circuits note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is significant. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 178 october 24, 2011 3 / ( ? , h ? 5 7 h 5 , h 5 , h 5 , h 7 $ , h $ 5 3 / ( f f , e 3 $ f , e 3 h 3 $ 3 , ) h 3 , , ) 9 , , i , e , 3 $ i i 3 0 8 3 8 g i ; , h ; 3 uart module block diagram ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 179 october 24, 2011 uart module serial interface uart module features interconnected to holtek mcu via spi interface full-duplex, universal asynchronous receiver and transmitter (uart) communication 8 or 9 bit character length even, odd or no parity options one or two stop bits baud rate generator with 8-bit prescaler parity, framing, noise and overrun error detection support for interrupt on address detect address detect interrupt - last character bit=1 transmitter and receiver enabled independently 4-byte deep fifo receiver data buffer transmit and receive multiple interrupt genera - tion sources: transmitter empty transmitter idle receiver full receiver overrun address mode detect tx pin is high impedance when the uart transmit module is disabled rx pin is high impedance when the uart receive module is disabled cmos clock input, clki, up to 20mhz at 5v operating voltage uart module overview the device contains a fully embedded full-duplex asyn - chronous serial communications uart interface that enables data transmission and data reception with ex - ternal devices. possible applications could include data communication networks between microcontrollers, low-cost data links between pcs and peripheral devices, portable and battery operated device commu - nication, factory automation and process control to name but a few. pin assignment ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 180 october 24, 2011 ! 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" # $ % % % % % % % % % % # % # ( % # % # ) % # % # % # * # ' % + , ' # % + # , % + * , % + # * , & # & & & % + * , % + # * # , % - % + , % - # % $ * # % - # % $ * % - & % + $ * , & % + * # , $ # % & $ % $ % $ % $ % & % + # , & % + , % + , % + % , $ % + % , $ % + , uart module pin description pin name i/o description rx i uart rx serial data input pin if uarten=1 and rxen=1, then rx is the uart serial data input if uarten=0 or rxen=0, then rx is high impedance tx o uart tx serial data output pin if uarten=1 and txen=1, then tx is the uart serial data output if uarten=0 or txen=0, then tx is high impedance sdi i slave spi serial data in input signal internally connected to the mcu master spi sdo output signal sdo o slave spi serial data out output signal internally connected to the mcu master spi sdi input signal sck i slave spi serial clock input signal internally connected to the mcu master spi sck output signal scs i slave spi device select input signal internally connected to the mcu master spi scs output signal - connected to pull high resistor clki i clock input signal internally connected to the mcu master pck output signal int o uart interrupt output signal internally connected to the mcu master pint input signal a uart related interrupt will generate a low pulse signal on this line nc implies that the pin is not connected and can therefore not be used. notes: the pin description for all pins with the exception of the uart tx and rx pins are described in the preceding mcu section. uart module d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions i dd1 operating current * (spi enabled, uart disabled) 3.0v f clki =12mhz, sck=f clki /4, output no load 1.0 ma 5.0v f clki =16mhz, sck=f clki /4, output no load 2.0 ma i dd2 operating current * (spi enabled, uart enabled) 2.2v f clki =6mhz, sck=f clki /4, output no load 4.2 ma 5.0v f clki =12mhz, sck=f clki /4, output no load 4.8 ma i stb standby current * (spi disabled, uart disabled) 5.0v f clki =16mhz, sck=f clki /4, scs =v dd , uarten=0, txen=1, rxen=1, sdi=h, rx=h, output no load 0.6 a v il input low voltage for rx ports 0 0.3v dd v v ih input high voltage for rx ports 0.7v dd v dd v i ol tx port sink current 3.0v v o =0.1v dd 2.5 5.0 ma 5.0v 10.0 25.0 ma i oh rx port source current 3.0v v o =0.9v dd 1.5 3.0 ma 5.0v 5.0 8.0 ma ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 182 october 24, 2011 symbol parameter test conditions min. typ. max. unit v dd conditions r ph pull-high resistance for scs only 3.0v 20 60 100 k 5.0v 10 30 50 k note: * the operating current i dd1 listed here is the additional current consumed when the slave spi interface in the uart module is enabled and the uart interface is disabled. similarly, the operating current i dd2 here is the additional current consumed when both the slave spi interface and uart interface are enabled. if the uart module is enabled, either i dd1 or i dd2 should be added to calculate the relevant operating current of the device for different conditions. to calculate the standby current for the whole device, the standby current shown above should be taken into account. uart module a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions t cp sck period (t ch +t cl ) 3.0v 62.5 ns 5.0v 50.0 ns t ch sck high time 3.0v 28 ns 5.0v 22 ns t cl sck low time 3.0v 28 ns 5.0v 22 ns t csw scs high pulse width 3.0v 500 ns 5.0v 400 ns t css scs to sck setup time 100 ns t csh scs to sck hold time 0 ns t sds sdi to sck setup time 100 ns t sdh sdi to sck hold time 0 ns t r spi output rise time 10 ns t f spi output fall time 10 ns t w spi data output delay time 0 ns ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 183 october 24, 2011 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 184 october 24, 2011 uart module functional description the embedded uart module is full-duplex asynchron - ous serial communications uart interface that enables communication with external devices that contain a se - rial interface. the uart function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmis - sion as well as being able to detect errors when the data is overwritten or incorrectly framed. interconnection be - tween the mcu and the uart module is implemented by internally connecting the mcu master spi interface to the uart slave spi interface. all data transmissions and receptions between mcu and uart module in - cluding uart commands are conducted along this in - terconnected spi interface. the uart function control is executed by the mcu using its spi master serial inter - face. the uart module contains its own independent interrupt which can be used to indicate when a data re - ception occurs or when a data transmission has termi - nated. uart module internal signal in addition to the tx and rx external pins described above there are other mcu to uart module intercon - necting lines that are described in the following table. note that these lines are internal to the device and are not bonded to external pins. uart module spi interface the mcu communicates with the uart module via an internal spi interface. the spi interface on this device is comprised of four signals: scs (spi chip select), sck (spi clock), sdi (serial data input) and sdo (serial data output). the spi master, which is the mcu, as - serts scs by pulling it low to start the data transaction cycle. when the first 8 bits of data are transmitted, scs should not return to a high level. instead, scs must re - main at a low level until the whole 16-bit data transaction is completed. if scs is de-asserted, that is returned to a high level before the 16-bit data transaction is com - pleted, all data bits will be discarded by the uart mod - ule spi slave. spi timing both read and write operations are conducted along the spi common interface with the following format: write type format: 8-bit command input + 8-bit data input read type format: 8-bit command input + 8-bit data output to initiate a data transaction, the mcu master spi needs to pull scs to a low level first and then also pull sck low. the input data bit on sdi should be stable be- fore the next sck rising edge, as the device will latch the sdi status on the next sck rising edge. regarding the sdo line, the output data bit will be updated on the sck falling edge. the master needs to obtain the line status before the next sck falling edge. there are 16 bits of data transmitted and/or received by the spi interface for each transaction. each transaction consists of a command phase and a data phase. when scs is high, the spi interface is disabled and sdo will be set to a high impedance state. after a complete transaction has been implemented, which requires 16 sck clock cycles, the master needs to set scs to a high level in preparation for the next data transaction. for write operations, the device will begin to execute the command only after it receives a 16-bit serial data se - quence and when the scs has been set high again by the master. ! mcu to uart internal connection ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 185 october 24, 2011 for read operations, the device will begin to execute the command only after it receives an 8-bit read command after which it will be ready to output data. if necessary, the master can de-assert the scs pin to abort the trans - action at any time which will cause any data transac - tions to be abandoned. uart module external pin interfacing to communicate with an external serial interface, the in - ternal uart has two external pins known as tx and rx. the tx pin is the uart transmitter serial data output pin if the corresponding control bits named uarten in ucr1 register and txen in ucr2 register are set to 1. if the control bit uarten or txen is equal to zero, the tx pin is in the state of high impedance. similarly, the rx pin is the uart receiver serial data input pin if the corresponding control bits named uarten and rxen in ucr1 and ucr2 registers are set to 1. if the control bit uarten or rxen is equal to zero, the rx pin is in the state of high impedance. uart data transfer scheme the following block diagram shows the overall data transfer structure arrangement for the uart. the actual data to be transmitted from the mcu is first transferred to the txr register by the application program. the data will then be transferred to the transmitter shift register named tsr from where it will be shifted out, lsb first, onto the tx pin at a rate controlled by the baud rate generator. only the txr register is accessible to the application program, the transmitter shift register is not mapped into the data memory area and is inacces - sible to the application program. data to be received by the uart is accepted on the ex - ternal rx pin, from where it is shifted in, lsb first, to the receiver shift register named rsr at a rate controlled by the baud rate generator. when the shift register is full, the data will then be transferred from the shift regis - ter to the internal rxr register, where it is buffered and can be manipulated by the application program. only the rxr register is accessible to the application pro - gram, the receiver shift register is not mapped into the data memory area and is inaccessible to the application program. it should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate txr and rxr registers, only exists as a single shared regis - ter physically. this shared register known as the txr/rxr register is used for both data transmission and data reception. sdo sdi sck scs a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 writing type format: 8-bit command input + 8-bit data input sdo sdi sck scs a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 t w reading type format: 8-bit command input + 8-bit data output msb lsb transmitter shift register (tsr) msb lsb receiver shift register (rsr) tx pin rx pin baud rate generator tx register (txr) rx register (rxr) buffer 1 buffer 2 buffer 3 data to be transmitted data received uart data transfer scheme ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 186 october 24, 2011 uart commands there are both read and write commands for the uart module. for reading and writing to registers both command and address information is contained within a single byte. the format for reading and writing is shown in the following table. command type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read fifo 00000xxx read register 00010a2a1a0 write fifo 00001xxx write register 00011a2a1a0 note: x here stands for don t care uart status and control registers there are six registers associated with the uart function. the usr, ucr1, ucr2 and ucr3 registers control the overall function of the uart module, while the brg register controls the baud rate. the actual data to be transmitted and received on the serial interface is managed through the txr/rxr data register. a[2:0] name reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h usr 0000 1011 perr nf ferr oerr ridle rxif tidle txif 01h ucr1 0000 0x00 uarten bno pren prt stops txbrk rx8 tx8 02h ucr2 0000 0000 txen rxen brgh adden wake rie tiie teie 03h brg xxxx xxxx brg7 brg6 brg5 brg4 brg3 brg2 brg1 brg0 04h ucr3 0 urst 05h~ 07h unused reserved uart register summary usr register the usr register is the status register for the uart, which can be read by the application program to determine the present status of the uart. all flags within the usr register are read only. further explanation on each of the flags is given below: bit76543210 name perr nf ferr oerr ridle rxif tidle txif r/wrrrrrrrr por00001011 bit 7 perr : parity error flag 0: no parity error is detected 1: parity error is detected the perr flag is the parity error flag. when this read only flag is 0 , it indicates a parity error has not been detected. when the flag is 1 , it indicates that the parity of the received word is incorrect. this error flag is applicable only if parity mode (odd or even) is selected. the flag can also be cleared by a software sequence which involves a read to the status register usr followed by an access to the rxr data register. bit 6 nf : noise flag 0: no noise is detected 1: noise is detected the nr flag is the noise flag. when this read only flag is 0 , it indicates no noise condition. when the flag is 1 , it indicates that the uart has detected noise on the receiver input. the nf flag is set during the same cycle as the rxif flag but will not be set in the case of as overrun. the nf flag can be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 187 october 24, 2011 bit 5 ferr : framing error flag 0: no framing error is detected 1: framing error is detected the ferr flag is the framing error flag. when this read only flag is 0 , it indicates that there is no framing error. when the flag is 1 , it indicates that a framing error has been detected for the current character. the flag can also be cleared by a software sequence which will involve a read to the status register usr followed by an access to the rxr data register. bit 4 oerr : overrun error flag 0: no overrun error is detected 1: overrun error is detected the oerr flag is the overrun error flag which indicates when the receiver buffer has overflowed. when this read only flag is 0 , it indicates that there is no overrun error. when the flag is 1 , it indicates that an overrun error occurs which will inhibit further transfers to the rxr receive data register. the flag is cleared by a software sequence, which is a read to the status register usr followed by an access to the rxr data register. bit 3 ridle : receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) the ridle flag is the receiver status flag. when this read only flag is 0 , it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. when the flag is 1 , it indicates that the receiver is idle. between the completion of the stop bit and the detection of the next start bit, the ridle bit is 1 indicating that the uart receiver is idle and the rx pin stays in logic high condition. bit 2 rxif : receive rxr data register status 0: rxr data register is empty 1: rxr data register has available data the rxif flag is the receive data register status flag. when this read only flag is 0 , it indicates that the rxr read data register is empty. when the flag is 1 , it indicates that the rxr read data register contains new data. when the contents of the shift register are transferred to the rxr register, an interrupt is generated if rie=1 in the ucr2 register. if one or more errors are detected in the received word, the appropriate receive-related flags nf, ferr, and/or perr are set within the same clock cycle. the rxif flag is cleared when the usr register is read with rxif set, followed by a read from the rxr register, and if the rxr register has no data available. bit 1 tidle : transmission idle 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) the tidle flag is known as the transmission complete flag. when this read only flag is 0 ,it indicates that a transmission is in progress. this flag will be set to 1 when the txif flag is 1 and when there is no transmit data or break character being transmitted. when tidle is equal to 1 , the tx pin becomes idle with the pin state in logic high condition. the tidle flag is cleared by reading the usr register with tidle set and then writing to the txr register. the flag is not generated when a data character or a break is queued and ready to be sent. bit 0 txif : transmit txr data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (txr data register is empty) the txif flag is the transmit data register empty flag. when this read only flag is 0 ,it indicates that the character is not transferred to the transmitter shift register. when the flag is 1, it indicates that the transmitter shift register has received a character from the txr data register. the txif flag is cleared by reading the uart status register (usr) with txif set and then writing to the txr data register. note that when the txen bit is set, the txif flag bit will also be set since the transmit data register is not yet full. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 188 october 24, 2011 ucr1 register the ucr1 register together with the ucr2 register are the two uart control registers that are used to set the vari - ous options for the uart function such as overall on/off control, parity control, data transfer bit length, etc. further explanation on each of the bits is given below: bit76543210 name uarten bno pren prt stops txbrk rx8 tx8 r/w r/w r/w r/w r/w r/w r/w r w por000000x0 x unknown bit 7 uarten : uart function enable control 0: disable uart. tx and rx pins are in the state of high impedance 1: enable uart. tx and rx pins function as uart pins the uarten bit is the uart enable bit. when this bit is equal to 0 , the uart will be disabled and the rx pin as well as the tx pin will be in the state of high impedance. when the bit is equal to 1 , the uart will be enabled and the tx and rx pins will function as defined by the txen and rxen enable control bits. when the uart is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. in addition, the value of the baud rate counter will be reset. if the uart is disabled, all error and status flags will be reset. also the txen, rxen, txbrk, rxif, oerr, ferr, perr and nf bits will be cleared, while the tidle, txif and ridle bits will be set. other control bits in ucr1, ucr2 and brg registers will remain unaffected. if the uart is active and the uarten bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. when the uart is re-enabled, it will restart in the same configuration. bit 6 bno : number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer this bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. when this bit is equal to 1 , a 9-bit data length format will be selected. if the bit is equal to 0 , then an 8-bit data length format will be selected. if 9-bit data length format is selected, then bits rx8 and tx8 will be used to store the 9th bit of the received and transmitted data respectively. bit 5 pren : parity function enable control 0: parity function is disabled 1: parity function is enabled this is the parity enable bit. when this bit is equal to 1 , the parity function will be enabled. if the bit is equal to 0 , then the parity function will be disabled. bit 4 prt : parity type selection bit 0: even parity for parity generator 1: odd parity for parity generator this bit is the parity type selection bit. when this bit is equal to 1 , odd parity type will be selected. if the bit is equal to 0 , then even parity type will be selected. bit 3 stops : number of stop bits selection 0: one stop bit format is used 1: two stop bits format is used this bit determines if one or two stop bits are to be used. when this bit is equal to 1 , two stop bits are used. if this bit is equal to 0 , then only one stop bit is used. bit 2 txbrk : transmit break character 0: no break character is transmitted 1: break characters transmit the txbrk bit is the transmit break character bit. when this bit is 0 , there are no break characters and the tx pin operates normally. when the bit is 1 , there are transmit break characters and the transmitter will send logic zeros. when this bit is equal to 1 , after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the txbrk bit is reset. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 189 october 24, 2011 bit 1 rx8 : receive data bit 8 for 9-bit data transfer format (read only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as rx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. bit 0 tx8 : transmit data bit 8 for 9-bit data transfer format (write only) this bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as tx8. the bno bit is used to determine whether data transfers are in 8-bit or 9-bit format. ucr2 register the ucr2 register is the second of the uart control registers and serves several purposes. one of its main func - tions is to control the basic enable/disable operation if the uart transmitter and receiver as well as enabling the various uart interrupt sources. the register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. further explanation on each of the bits is given below: bit76543210 name txen rxen brgh adden wake rie tiie teie r/w r/w r/w r/w r/w r/w r/w r w por00001011 bit 7 txen : uart transmitter enable control 0: uart transmitter is disabled 1: uart transmitter is enabled the bit named txen is the transmitter enable bit. when this bit is equal to 0 , the transmitter will be disabled with any pending data transmissions being aborted. in addition the buffers will be reset. in this situation the tx pin will be in the state of high impedance. if the txen bit is equal to 1 and the uarten bit is also equal to 1 , the transmitter will be enabled and the tx pin will be controlled by the uart. clearing the txen bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. if this situation occurs, the tx pin will be in the state of high impedance. bit 6 rxen : uart receiver enable control 0: uart receiver is disabled 1: uart receiver is enabled the bit named rxen is the receiver enable bit. when this bit is equal to 0 , the receiver will be disabled with any pending data receptions being aborted. in addition the receive buffers will be reset. in this situation the rx pin will be in the state of high impedance. if the rxen bit is equal to 1 and the uarten bit is also equal to 1 , the receiver will be enabled and the rx pin will be controlled by the uart. clearing the rxen bit during a reception will cause the data reception to be aborted and will reset the receiver. if this situation occurs, the rx pin will be in the state of high impedance. bit 5 brgh : baud rate speed selection 0: low speed baud rate 1: high speed baud rate the bit named brgh selects the high or low speed mode of the baud rate generator. this bit, together with the value placed in the baud rate register brg, controls the baud rate of the uart. if this bit is equal to 1 , the high speed mode is selected. if the bit is equal to 0, the low speed mode is selected. bit 4 adden : address detect function enable control 0: address detect function is disabled 1: address detect function is enabled the bit named adden is the address detect function enable control bit. when this bit is equal to 1 , the address detect function is enabled. when it occurs, if the 8th bit, which corresponds to rx7 if bno=0 or the 9th bit, which corresponds to rx8 if bno=1, has a value of 1, then the received word will be identified as an address, rather than data. if the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of bno. if the address bit known as the 8th or 9th bit of the received word is 0 with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 190 october 24, 2011 bit 3 wake : rx pin falling edge wake-up function enable control 0: rx pin wake-up function is disabled 1: rx pin wake-up function is enabled this bit enables or disables the receiver wake-up function. if this bit is equal to 1 and the mcu is in idle or sleep mode, a falling edge on the rx input pin will wake-up the device. if this bit is equal to 0 and the mcu is in idle or sleep mode, any edge transitions on the rx pin will not wake-up the device. bit 2 rie : receiver interrupt enable control 0: receiver related interrupt is disabled 1: receiver related interrupt is enabled this bit enables or disables the receiver interrupt. if this bit is equal to 1 and when the receiver overrun flag oerr or receive data available flag rxif is set, the uart interrupt request flag will be set. if this bit is equal to 0 , the uart interrupt request flag will not be influenced by the condition of the oerr or rxif flags. bit 1 tiie : transmitter idle interrupt enable control 0: transmitter idle interrupt is disabled 1: transmitter idle interrupt is enabled this bit enables or disables the transmitter idle interrupt. if this bit is equal to 1 and when the transmitter idle flag tidle is set, due to a transmitter idle condition, the uart interrupt request flag will be set. if this bit is equal to 0 , the uart interrupt request flag will not be influenced by the condition of the tidle flag. bit 0 teie : transmitter empty interrupt enable control 0: transmitter empty interrupt is disabled 1: transmitter empty interrupt is enabled this bit enables or disables the transmitter empty interrupt. if this bit is equal to 1 and when the transmitter empty flag txif is set, due to a transmitter empty condition, the uart interrupt request flag will be set. if this bit is equal to 0 , the uart interrupt request flag will not be influenced by the condition of the txif flag. ucr3 register the ucr3 register is the last of the uart control registers and controls the software reset operation of the uart module. the only one available bit named urst in the uart control register ucr3 is the uart software reset con- trol bit. when this bit is equal to 0 , the uart operates normally. if this bit is equal to 1 , the whole uart module will be reset. when this situation occurs, the transmitter and receiver will be reset. the uart registers including the status register and control registers will keep the por states shown in the above uart registers table after the reset condition occurs. bit76543210 name urst r/w r/w por 0 bit 7 urst : uart software reset 0: no action 1: uart reset occurs bit 6~0 unimplemented, read as 0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 191 october 24, 2011 baud rate generator to setup the speed of the serial data communication, the uart function contains its own dedicated baud rate generator. the baud rate is controlled by its own internal free running 8-bit timer, the period of which is deter - mined by two factors. the first of these is the value placed in the baud rate register brg and the second is the value of the brgh bit with the control register ucr2. the brgh bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to cal - culate the baud rate. the value n in the brg register which is used in the following baud rate calculation for - mula determines the division factor. note that n is the decimal value placed in the brg register and has a range of between 0 and 255. ucr2 brgh bit 0 1 baud rate (br) f [64 (n+1)] clki f [16 (n+1)] clki by programming the brgh bit which allows selection of the related formula and programming the required value in the brg register, the required baud rate can be setup. note that because the actual baud rate is deter - mined using a discrete value, n, placed in the brg reg- ister, there will be an error associated between the actual and requested value. the following example shows how the brg register value n and the error value can be calculated. calculating the baud rate and error values for a clock frequency of 4mhz, and with brgh set to 0 determine the brg register value n, the actual baud rate and the error value for a desired baud rate of 4800. from the above table the desired baud rate br = f [64 (n+1)] clki re-arranging this equation gives n = f (brx64) clki 1 giving a value for n = 4000000 4800 64 () x 1 12.0208 to obtain the closest value, a decimal value of 12 should be placed into the brg register. this gives an actual or calculated baud rate value of br= 4000000 [64(12+1)] 4808 therefore the error is equal to = 0.16% ! # ! ! # # ! # # the following tables show the actual values of baud rate and error values for the two value of brgh. baud rate k/bps baud rates for brgh=0 f clki =4mhz f clki =3.579545mhz f clki =7.159mhz brg kbaud error (%) brg kbaud error (%) brg kbaud error (%) 0.3 207 0.300 0.16 185 0.300 0.00 1.2 51 1.202 0.16 46 1.190 0.83 92 1.203 0.23 2.4 25 2.404 0.16 22 2.432 1.32 46 2.380 0.83 4.8 12 4.808 0.16 11 4.661 2.90 22 4.863 1.32 9.6 6 8.929 6.99 5 9.321 2.90 11 9.322 2.90 19.2 2 20.833 8.51 2 18.643 2.90 5 18.643 2.90 38.4 2 32.286 2.90 57.6 0 62.500 8.51 0 55.930 2.90 1 55.930 2.90 115.2 0 111.859 2.90 baud rates and error values for brgh 0 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 192 october 24, 2011 baud rate k/bps baud rates for brgh=1 f clki =4mhz f clki =3.579545mhz f clki =7.159mhz brg kbaud error (%) brg kbaud error (%) brg kbaud error (%) 0.3 1.2 207 1.202 0.16 185 1.203 0.23 2.4 103 2.404 0.16 92 2.406 0.23 185 2.406 0.23 4.8 51 4.808 0.16 46 4.76 0.83 92 4.811 0.23 9.6 25 9.615 0.16 22 9.727 1.32 46 9.520 0.83 19.2 12 19.231 0.16 11 18.643 2.90 22 19.454 1.32 38.4 6 35.714 6.99 5 37.286 2.90 11 37.286 2.90 57.6 3 62.5 8.51 3 55.930 2.90 7 55.930 2.90 115.2 1 125 8.51 1 111.86 2.90 3 111.86 2.90 250 0 250 0 baud rates and error values for brgh 1 brg register bit76543210 name brg7 brg6 brg5 brg4 brg3 brg2 brg1 brg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w porxxxxxxxx x : unknown bit 7~0 brg7~brg0: baud rate values by programming the brgh bit in ucr2 register which allows selection of the related formula described above and programming the required value in the brg register, the required baud rate can be setup. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 193 october 24, 2011 uart module setup and control for data transfer, the uart function utilizes a non-return-to-zero, more commonly known as nrz, for - mat. this is composed of one start bit, eight or nine data bits and one or two stop bits. parity is supported by the uart hardware and can be setup to be even, odd or no parity. for the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, n, 1, is used as the default setting, which is the setting at power-on. the number of data bits and stop bits, along with the parity, are setup by programming the corre - sponding bno, prt, pren and stops bits in the ucr1 register. the baud rate used to transmit and re - ceive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received lsb first. although the transmitter and receiver of the uart are functionally independent, they both use the same data format and baud rate. in all cases stop bits will be used for data transmission. enabling/disabling the uart the basic on/off function of the internal uart function is controlled using the uarten bit in the ucr1 regis - ter. if the uarten, txen and rxen bits are set, then these two uart pins will act as normal tx output pin and rx input pin respectively. if no data is being trans - mitted on the tx pin, then it will default to a logic high value. clearing the uarten bit will disable the tx and rx pins and these two pins will be in the state of high im- pedance. when the uart function is disabled, the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. dis- abling the uart will also reset the enable control, the error and status flags with bits txen, rxen, txbrk, rxif, oerr, ferr, perr and nf being cleared while bits tidle, txif and ridle will be set. the re - maining control bits in the ucr1, ucr2 and brg reg - isters will remain unaffected. if the uarten bit in the ucr1 register is cleared while the uart is active, then all pending transmissions and receptions will be immediately suspended and the uart will be reset to a condition as defined above. if the uart is then sub - sequently re-enabled, it will restart again in the same configuration. data, parity and stop bit selection the format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. these factors are determined by the setup of various bits within the ucr1 register. the bno bit controls the number of data bits which can be set to either 8 or 9. the prt bit controls the choice if odd or even parity. the pren bit controls the parity on/off function. the stops bit decides whether one or two stop bits are to be used. the following table shows various formats for data transmission. the address detect mode con - trol bit identifies the frame as an address character. the number of stop bits, which can be either one or two, is independent of the data length. start bit data bits address bits parity bits stop bit example of 8-bit data formats 18001 17011 17101 example of 9-bit data formats 19001 18011 18101 transmitter receiver data format the following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. $ / $ / # $ / $ / $ / $ / $ / $ / $ / 0 1 $ / 2 $ / / 3 $ / " # $ % $ % & ' % $ $ / $ / # $ / $ / $ / $ / $ / $ / $ / 0 1 $ / 2 $ / / 3 $ / ( " # $ % $ % & ' % $ $ / ! ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 194 october 24, 2011 uart transmitter data word lengths of either 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, needs to be stored in the tx8 bit in the ucr1 register. at the transmitter core lies the transmitter shift register, more commonly known as the tsr, whose data is ob - tained from the transmit data register, which is known as the txr register. the data to be transmitted is loaded into this txr register by the application pro - gram. the tsr register is not written to with new data until the stop bit from the previous transmission has been sent out. as soon as this stop bit has been trans - mitted, the tsr can then be loaded with new data from the txr register, if it is available. it should be noted that the tsr register, unlike many other regis - ters, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. an actual transmis - sion of data will normally be enabled when the txen bit is set, but the data will not be transmitted until the txr register has been loaded with data and the baud rate generator has defined a shift clock source. how - ever, the transmission can also be initiated by first loading data into the txr register, after which the txen bit can be set. when a transmission of data be - gins, the tsr is normally empty, in which case a transfer to the txr register will result in an immediate transfer to the tsr. if during a transmission the txen bit is cleared, the transmission will immediately cease and the transmitter will be reset. the tx output pin will then return to the high impedance state. transmitting data when the uart is transmitting data, the data is shifted on the tx pin from the shift register, with the least significant bit lsb first. in the transmit mode, the txr register forms a buffer between the internal bus and the transmitter shift register. it should be noted that if 9-bit data format has been selected, then the msb will be taken from the tx8 bit in the ucr1 regis - ter. the steps to initiate a data transfer can be sum - marized as follows: make the correct selection of the bno, prt, pren and stops bits to define the required word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the txen bit to ensure that the uart transmit - ter is enabled and the tx pin is used as a uart transmitter pin. access the usr register and write the data that is to be transmitted into the txr register. note that this step will clear the txif bit. this sequence of events can now be repeated to send additional data. it should be noted that when txif=0, data will be in - hibited from being written to the txr register. clear - ing the txif flag is always achieved using the following software sequence: 1. a usr register access 2. a txr register write execution the read-only txif flag is set by the uart hardware and if set indicates that the txr register is empty and that other data can now be written into the txr regis - ter without overwriting the previous data. if the teie bit is set, then the txif flag will generate an interrupt. during a data transmission, a write instruction to the txr register will place the data into the txr register, which will be copied to the shift register at the end of the present transmission. when there is no data transmission in progress, a write instruction to the txr register will place the data directly into the shift register, resulting in the commencement of data trans - mission, and the txif bit being immediately set. when a frame transmission is complete, which hap - pens after stop bits are sent or after the break frame, the tidle bit will be set. to clear the tidle bit the fol - lowing software sequence is used: 1. a usr register access 2. a txr register write execution note that both the txif and tidle bits are cleared by the same software sequence. transmitting break if the txbrk bit is set, then the break characters will be sent on the next transmission. break character transmission consists of a start bit, followed by 13 n 0 bits, where n=1, 2, etc. if a break character is to be transmitted, then the txbrk bit must be first set by the application program and then cleared to generate the stop bits. transmitting a break character will not generate a transmit interrupt. note that a break condi - tion length is at least 13 bits long. if the txbrk bit is continually kept at a logic high level, then the transmit - ter circuitry will transmit continuous break characters. after the application program has cleared the txbrk bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. the automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 195 october 24, 2011 uart receiver the uart is capable of receiving word lengths of ei - ther 8 or 9 bits can be selected by programming the bno bit in the ucr1 register. when bno bit is set, the word length will be set to 9 bits. in this case the 9th bit, which is the msb, will be stored in the rx8 bit in the ucr1 register. at the receiver core lies the receiver shift register more commonly known as the rsr. the data which is received on the rx external input pin is sent to the data recovery block. the data recov - ery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. after the rx pin is sampled for the stop bit, the received data in rsr is transferred to the re - ceive data register, if the register is empty. the data which is received on the external rx input pin is sam - pled three times by a majority detect circuit to deter - mine the logic level that has been placed onto the rx pin. it should be noted that the rsr register, unlike many other registers, is not directly mapped into the data memory area and as such is not available to the application program for direct read/write operations. receiving data when the uart receiver is receiving data, the data is serially shifted in on the external rx input pin to the shift register, with the least significant bit lsb first. the rxr register is a four byte deep fifo data buffer, where four bytes can be held in the fifo while the 5th byte can continue to be received. note that the appli- cation program must ensure that the data is read from rxr before the 5th byte has been completely shifted in, otherwise the 5th byte will be discarded and an overrun error oerr will be subsequently indicated. the steps to initiate a data transfer can be summa- rized as follows: make the correct selection of the bno, prt, pren and stops bits to define the required word length, parity type and number of stop bits. setup the brg register to select the desired baud rate. set the rxen bit to ensure that the uart receiver is enabled and the rx pin is used as a uart re - ceiver pin. at this point the receiver will be enabled which will be - gin to look for a start bit. when a character is received, the following sequence of events will occur: the rxif bit in the usr register will be set then rxr register has data available, at least three more character can be read. when the contents of the shift register have been transferred to the rxr register and if the rie bit is set, then an interrupt will be generated. if during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error flags can be set. the rxif bit can be cleared using the following soft - ware sequence: 1. a usr register access 2. a rxr register read execution receiving break any break character received by the uart will be managed as a framing error. the receiver will count and expect a certain number of bit times as specified by the values programmed into the bno and stops bits. if the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by bno and stops. the rxif bit is set, ferr is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the ridle bit is set. if a long break signal has been detected and the receiver has re - ceived a start bit, the data bits and the invalid stop bit, which sets the ferr flag, the receiver must wait for a valid stop bit before looking for the next start bit. the receiver will not make the assumption that the break condition on the line is the next start bit. a break is re - garded as a character that contains only zeros with the ferr flag set. the break character will be loaded into the buffer and no further data will be received until stop bits are received. it should be noted that the ridle read only flag will go high when the stop bits have not yet been received. the reception of a break character on the uart registers will result in the fol - lowing: the framing error flag, ferr, will be set. the receive data register, rxr, will be cleared. the oerr, nf, perr, ridle or rxif flags will possibly be set. idle status when the receiver is reading data, which means it will be in between the detection of a start bit and the read- ing of a stop bit, the receiver status flag in the usr register, otherwise known as the ridle flag, will have a zero value. in between the reception of a stop bit and the detection of the next start bit, the ridle flag will have a high value, which indicates the receiver is in an idle condition. receiver interrupt the read only receive interrupt flag rxif in the usr register is set by an edge generated by the receiver. an interrupt is generated if rie=1, when a word is transferred from the receive shift register, rsr, to the receive data register, rxr. an overrun error can also generate an interrupt if rie=1. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 196 october 24, 2011 managing receiver errors several types of reception errors can occur within the uart module, the following section describes the vari - ous types and how they are managed by the uart. overrun error oerr flag the rxr register is composed of a four byte deep fifo data buffer, where four bytes can be held in the fifo register, while a 5th byte can continue to be re - ceived. before the 5th byte has been entirely shifted in, the data should be read from the rxr register. if this is not done, the overrun error flag oerr will be consequently indicated. in the event of an overrun error occurring, the follow - ing will happen: the oerr flag in the usr register will be set. the rxr contents will not be lost. the shift register will be overwritten. an interrupt will be generated if the rie bit is set. the oerr flag can be cleared by an access to the usr register followed by a read to the rxr register. noise error nf flag over-sampling is used for data recovery to identify valid incoming data and noise. if noise is detected within a frame, the following will occur: the read only noise flag, nf, in the usr register will be set on the rising edge of the rxif bit. data will be transferred from the shift register to the rxr register. no interrupt will be generated. however this bit rises at the same time as the rxif bit which itself generates an interrupt. note that the nf flag is reset by a usr register read operation followed by an rxr register read operation. framing error ferr flag the read only framing error flag, ferr, in the usr register, is set if a zero is detected instead of stop bits. if two stop bits are selected, both stop bits must be high. otherwise the ferr flag will be set. the ferr flag is buffered along with the received data and is cleared in any reset. parity error perr flag the read only parity error flag, perr, in the usr reg - ister, is set if the parity of the received word is incor - rect. this error flag is only applicable if the parity function is enabled, pren=1, and if the parity type, odd or even, is selected. the read only perr flag is buffered along with the received data bytes. it is cleared on any reset, it should be noted that the ferr and perr flags are buffered along with the corre - sponding word and should be read before reading the data word. uart module interrupt structure several individual uart conditions can generate a uart interrupt. when these conditions exist, a low pulse will be generated on the int line to get the atten - tion of the microcontroller. these conditions are a trans - mitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an rx pin wake-up. when any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its correspond - ing interrupt vector where it can be serviced before re - turning to the main program. four of these conditions have the corresponding usr register flags which will generate a uart interrupt if its associated interrupt en - able control bit in the ucr2 register is set. the two transmitter interrupt conditions have their own corre - sponding enable control bits, while the two receiver in - terrupt conditions have a shared enable control bit. these enable bits can be used to mask out individual uart interrupt sources. the address detect condition, which is also a uart in - terrupt source, does not have an associated flag, but will generate a uart interrupt when an address detect con - dition occurs if its function is enabled by setting the adden bit in the ucr2 register. an rx pin wake-up, which is also a uart interrupt source, does not have an associated flag, but will generate a uart interrupt if the microcontroller is woken up by a falling edge on the rx pin, if the wake and rie bits in the ucr2 register are set. note that in the event of an rx wake-up interrupt occurring, there will be a certain period of delay, com- monly known as the system start-up time, for the oscil- lator to restart and stabilize before the system resumes normal operation. note that the usr register flags are read only and can - not be cleared or set by the application program, neither will they be cleared when the program jumps to the cor - responding interrupt servicing routine, as is the case for some of the other interrupts. the flags will be cleared automatically when certain actions are taken by the uart, the details of which are given in the uart regis - ter section. the overall uart interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the uart module is masked out or allowed. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 197 october 24, 2011 address detect mode setting the address detect function enable control bit, adden, in the ucr2 register, enables this special function. if this bit is set to 1 , then an additional qual- ifier will be placed on the generation of a receiver data available interrupt, which is requested by the rxif flag. if the adden bit is equal to 1 , then when the data is available, an interrupt will only be gener- ated, if the highest received bit has a high value. note that the related interrupt enable control bit and the emi bit of the microcontroller must also be enabled for correct interrupt generation. the highest address bit is the 9th bit if the bit bno=1 or the 8th bit if the bit bno=0. if the highest bit is high, then the received word will be defined as an address rather than data. a data available interrupt will be generated every time the last bit of the received word is set. if the adden bit is equal to 0 , then a receive data available interrupt will be generated each time the rxif flag is set, irre - spective of the data last but status. the address de - tect and parity functions are mutually exclusive functions. therefore if the address detect function is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit pren to zero. adden bit 9 if bno=1, bit 8 if bno=0 uart interrupt generated 0 0 1 1 0x 1 adden bit function uart module power-down and wake-up the mcu and uart module are powered down inde- pendently of each other. the method of powering down the mcu is covered in the previous mcu section of the datasheet. the uart module must be powered down before the mcu is powered down. this is implemented by first clearing the uarten bit in the ucr1 register to disable the uart module circuitry after which the scs internal line can be set high to disable the spi interface circuits. when the uart and spi interfaces are pow - ered down, the sck and clki clock sources to the uart module will be disabled. the uart module can be powered up by the mcu by first clearing the scs line to zero and then setting the uarten bit. if the uart circuits is powered down while a transmission is still in progress, then the transmission will be terminated and the external tx transmit pin will be forced to a logic high level. in a similar way, if the uart circuits is powered down while receiving data, then the reception of data will likewise be terminated. when the uart circuits is pow - ered down, note that the usr, ucr1, ucr2, ucr3, transmit and receive registers, as well as the brg regis - ter will not be affected. the uart module contains a receiver rx pin wake-up function, which is enabled or disabled by the wake bit in the ucr2 register. if this bit, along with the uart en - able bit named uarten, the receiver enable bit named rxen and the receiver interrupt enable bit named rie, are all set before the mcu and uart module are is powered down, then a falling edge on the rx pin will wake up the mcu from its power down condition. note 4 / 5 5 6 / & 6 1 3 ' 7 4 ' 5 6 / 8 7 ' 7 4 & / 9 9 / 7 : 7 ' / 9 9 ; ' 7 4 & / $ < # ! / $ < & # # / = > ( ; 1 = & # 4 / 5 & & & & 4 / 5 # # # 0 - / ; 1 / 1 ; uart interrupt structure ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 198 october 24, 2011 that as it takes a certain period of time known as the system start-up time for oscillator to restart and stabi - lize after a wake-up, any data received during this time on the rx pin will be ignored. for a uart wake-up interrupt to occur, in addition to the bits for the wake-up enable control and receive inter - rupt enable control being set, the global interrupt enable control and the related interrupt enable control bits must also be set. if these two bits are not set, then only a wake-up event will occur and no interrupt will be ser - viced. note also that as it takes a period of delay after a wake-up before normal microcontroller resumes, the relevant uart interrupt will not be serviced until this pe - riod of delay time has elapsed. using the uart function to use the uart function, several important steps must be implemented to ensure that the uart module oper - ates normally: the spi pin-remapping function must be properly configured when the spi functional pins of the microcontroller are used to control the uart module and for data transmission and data reception. to correctly connect the mcu master spi to the uart module slave spi, the sim pin-remapping settings for pck and pintb in the mcu prm0 register should be the same as the values listed in the following table. ht68fu30 prm0 register pck and pint pin-remap setup bit 1 0 name simps0 pckps setting value 1 1 ht68fu40/ht68fu50 prm0 register pck and pint pin-remap setup bit 2 1 0 name simps1 simps0 pckps setting value 0 1 1 ht68fu60 prm0 register pck and pint pin-remap setup bit 2 1 0 name simps1 simps0 pckps setting value 1 1 1 the sim operating mode control bits sim2~sim0, in the simc0 register have to be configured to enable the sim to operate in the spi master mode with a dif - ferent spi clock frequency. sim operating mode control bits sim2~sim0 in the simc0 register bit 7 6 5 name sim2 sim1 sim0 value 100, 011, 010, 001 or 000 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101~111: must not be used the pck control bit is set to 1 to enable the pck out - put as the clock source for the uart baud rate gener - ator with various pck output frequencies determined by the pckp1 and pckp0 bits in the simc0 register. pck output frequency selection bits pckp1~pckp0 in the simc0 register bit 3 2 name pckp1 pckp0 value 11, 10, 01 or 00 00: pck output frequency is f sys 01: pck output frequency is f sys /4 10: pck output frequency is f sys /8 11: pck output frequency is tm0 ccrp match frequency/2 pck output enable control bit pcken in the simc0 register bit 4 name pcken value 1 0: disable pck output 1: enable pck output after the above setup conditions have been imple - mented, the mcu can enable the sim interface by set - ting the simen bit high. the mcu can then begin communication with external uart connected devices using its spi interface. the detailed mcu master spi functional description is provided within the serial inter - face module section of the mcu datasheet. application circuit with uart module note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is significant. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 199 october 24, 2011 / ; / ) * # % $ & * $ # + 2 % 0 5 / ; / ) * # % $ & * $ # + & # ? ' ) $ ! # & * # $ # ? @ ' # > @ # # > # # a # ? # ' a a ! a 5 / 9 0 % ' 0 6 $ ; 5 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 200 october 24, 2011 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits. ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 201 october 24, 2011 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 202 october 24, 2011 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrd [m] tabrdl [m] read table to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 203 october 24, 2011 call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 204 october 24, 2011 cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 205 october 24, 2011 inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 206 october 24, 2011 or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 207 october 24, 2011 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 208 october 24, 2011 sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 209 october 24, 2011 siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 210 october 24, 2011 swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrd [m] read table to tblh and data memory description the program code addressed by the table pointer (tbhp and tblp) is moved to the speci - fied data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 211 october 24, 2011 xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 212 october 24, 2011 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regu - lar intervals users are reminded to consult the holtek website ( http://www.holtek.com.tw/english/literature/package.pdf ) for the latest version of the package information. 16-pin dip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in inch min. nom. max. a 0.780 0.880 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 19.81 22.35 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 213 october 24, 2011 fig1. full lead packages fig2. 1 / 2 lead packages ms-001d (see fig2) symbol dimensions in inch min. nom. max. a 0.735 0.775 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 18.67 19.69 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 214 october 24, 2011 mo-095a (see fig2) symbol dimensions in inch min. nom. max. a 0.745 0.785 b 0.275 0.295 c 0.120 0.150 d 0.110 0.150 e 0.014 0.022 f 0.045 0.060 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 18.92 19.94 b 6.99 7.49 c 3.05 3.81 d 2.79 3.81 e 0.36 0.56 f 1.14 1.52 g 2.54 h 7.62 8.26 i 10.92 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 215 october 24, 2011 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.012 0.020 c 0.386 0.402 d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.30 0.51 c 9.80 10.21 d 1.75 e 1.27 f 0.10 0.25 g 0.41 1.27 h 0.18 0.25 0 8 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 216 october 24, 2011 16-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.189 0.197 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 4.80 5.00 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 217 october 24, 2011 20-pin dip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in inch min. nom. max. a 0.980 1.060 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 24.89 26.92 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 218 october 24, 2011 fig1. full lead packages fig2. 1 / 2 lead packages mo-095a (see fig2) symbol dimensions in inch min. nom. max. a 0.945 0.985 b 0.275 0.295 c 0.120 0.150 d 0.110 0.150 e 0.014 0.022 f 0.045 0.060 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 24.00 25.02 b 6.99 7.49 c 3.05 3.81 d 2.79 3.81 e 0.36 0.56 f 1.14 1.52 g 2.54 h 7.62 8.26 i 10.92 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 219 october 24, 2011 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.496 0.512 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 12.60 13.00 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 220 october 24, 2011 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.158 c 0.008 0.012 c 0.335 0.347 d 0.049 0.065 e 0.025 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 4.01 c 0.20 0.30 c 8.51 8.81 d 1.24 1.65 e 0.64 f 0.10 0.25 g 0.38 1.27 h 0.18 0.25 0 8 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 221 october 24, 2011 24-pin skdip (300mil) outline dimensions ms-001d (see fig1) symbol dimensions in inch min. nom. max. a 1.230 1.280 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 31.24 32.51 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 222 october 24, 2011 fig1. full lead packages fig2. 1 / 2 lead packages ms-001d (see fig2) symbol dimensions in inch min. nom. max. a 1.160 1.195 b 0.240 0.280 c 0.115 0.195 d 0.115 0.150 e 0.014 0.022 f 0.045 0.070 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 29.46 30.35 b 6.10 7.11 c 2.92 4.95 d 2.92 3.81 e 0.36 0.56 f 1.14 1.78 g 2.54 h 7.62 8.26 i 10.92 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 223 october 24, 2011 mo-095a (see fig2) symbol dimensions in inch min. nom. max. a 1.145 1.185 b 0.275 0.295 c 0.120 0.150 d 0.110 0.150 e 0.014 0.022 f 0.045 0.060 g 0.100 h 0.300 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 29.08 30.10 b 6.99 7.49 c 3.05 3.81 d 2.79 3.81 e 0.36 0.56 f 1.14 1.52 g 2.54 h 7.62 8.26 i 10.92 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 224 october 24, 2011 24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.598 0.613 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 15.19 15.57 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 225 october 24, 2011 24-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.335 0.346 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 8.51 8.79 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 226 october 24, 2011 28-pin skdip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 1.375 1.395 b 0.278 0.298 c 0.125 0.135 d 0.125 0.145 e 0.016 0.020 f 0.050 0.070 g 0.100 h 0.295 0.315 i 0.375 symbol dimensions in mm min. nom. max. a 34.93 35.43 b 7.06 7.57 c 3.18 3.43 d 3.18 3.68 e 0.41 0.51 f 1.27 1.78 g 2.54 h 7.49 8.00 i 9.53 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 227 october 24, 2011 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.697 0.713 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 0 8 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 17.70 18.11 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 0 8 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 228 october 24, 2011 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.386 0.394 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 0 8 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 9.80 10.01 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 0 8 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 229 october 24, 2011 saw type 32-pin (5mm 5mm) qfn outline dimensions asecl symbol dimensions in inch min. nom. max. a 0.028 0.031 a1 0.000 0.001 0.002 a3 0.008 b 0.007 0.010 0.012 d 0.197 e 0.197 e 0.020 d2 0.122 0.130 e2 0.122 0.130 l 0.014 0.016 0.018 k 0.008 symbol dimensions in mm min. nom. max. a 0.70 0.80 a1 0.00 0.02 0.05 a3 0.20 b 0.18 0.25 0.30 d 5.00 e 5.00 e 0.50 d2 3.10 3.30 e2 3.10 3.30 l 0.35 0.40 0.45 k 0.20 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 230 october 24, 2011 saw type 40-pin (6mm 6mm for 0.75mm) qfn outline dimensions gtk symbol dimensions in inch min. nom. max. a 0.028 0.030 0.031 a1 0.000 0.001 0.002 a3 0.008 b 0.007 0.010 0.012 d 0.236 e 0.236 e 0.020 d2 0.173 0.177 0.179 e2 0.173 0.177 0.179 l 0.014 0.016 0.018 k 0.008 symbol dimensions in mm min. nom. max. a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 b 0.18 0.25 0.30 d 6.00 e 6.00 e 0.50 d2 4.40 4.50 4.55 e2 4.40 4.50 4.55 l 0.35 0.40 0.45 k 0.20 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 231 october 24, 2011 44-pin lqfp (10mm 10mm) (fp3.2mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.512 0.520 0.528 b 0.390 0.394 0.398 c 0.512 0.520 0.528 d 0.390 0.394 0.398 e 0.031 f 0.012 g 0.053 0.055 0.057 h 0.063 i 0.004 0.010 j 0.041 0.047 0.053 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 13.00 13.20 13.40 b 9.90 10.00 10.10 c 13.00 13.20 13.40 d 9.90 10.00 10.10 e 0.80 f 0.30 g 1.35 1.40 1.45 h 1.60 i 0.10 0.25 j 1.05 1.20 1.35 k 0.10 0.25 07 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 232 october 24, 2011 48-pin ssop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.395 0.420 b 0.291 0.299 c 0.008 0.012 c 0.613 0.637 d 0.085 0.099 e 0.025 f 0.004 0.010 g 0.025 0.035 h 0.004 0.012 08 symbol dimensions in mm min. nom. max. a 10.03 10.67 b 7.39 7.59 c 0.20 0.30 c 15.57 16.18 d 2.16 2.51 e 0.64 f 0.10 0.25 g 0.64 0.89 h 0.10 0.30 08 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 233 october 24, 2011 saw type 48-pin (7mm 7mm) qfn outline dimensions asecl symbol dimensions in inch min. nom. max. a 0.031 0.033 0.035 a1 0.000 0.001 0.002 a3 0.008 b 0.007 0.010 0.012 d 0.276 e 0.276 e 0.020 d2 0.219 0.222 0.226 e2 0.219 0.222 0.226 l 0.014 0.016 0.018 symbol dimensions in mm min. nom. max. a 0.800 0.850 0.900 a1 0.000 0.035 0.050 a3 0.203 b 0.180 0.250 0.300 d 7.000 e 7.000 e 0.500 d2 5.550 5.650 5.750 e2 5.550 5.650 5.750 l 0.350 0.400 0.450 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 234 october 24, 2011 48-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 235 october 24, 2011 52-pin qfp (14mm 14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.681 0.689 b 0.547 0.555 c 0.681 0.689 d 0.547 0.555 e 0.039 f 0.016 g 0.098 0.122 h 0.134 i 0.004 j 0.029 0.041 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 17.30 17.50 b 13.90 14.10 c 17.30 17.50 d 13.90 14.10 e 1.00 f 0.40 g 2.50 3.10 h 3.40 i 0.10 j 0.73 1.03 k 0.10 0.20 0 7 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 236 october 24, 2011 product tape and reel specifications reel dimensions sop 16n (150mil) symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.2 0.2 sop 20w, sop 24w, sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.2 0.2 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 237 october 24, 2011 ssop 16s symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 12.8 +0.3/-0.2 t2 reel thickness 18.2 0.2 ssop 20s (150mil), ssop 24s (150mil), ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.2 0.2 ssop 48w symbol description dimensions in mm a reel outer diameter 330.0 1.0 b reel inner diameter 100.0 0.1 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0 0.5 t1 space between flange 32.2 +0.3/-0.2 t2 reel thickness 38.2 0.2 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 238 october 24, 2011 carrier tape dimensions sop 16n (150mil) symbol description dimensions in mm w carrier tape width 16.0 0.3 p cavity pitch 8.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 10.3 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 sop 20w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.8 0.1 b0 cavity width 13.3 0.1 k0 cavity depth 3.2 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 21.3 0.1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 239 october 24, 2011 ! " # ! $ % & ! & ' ( ) * ( + * , ! ) * + " ! ' + & ( , ! - , % ' . / * + * sop 24w symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.9 0.1 b0 cavity width 15.9 0.1 k0 cavity depth 3.1 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 21.3 0.1 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.10 b0 cavity width 18.34 0.10 k0 cavity depth 2.97 0.10 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 0.1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 240 october 24, 2011 ssop 16s symbol description dimensions in mm w carrier tape width 12.0 +0.3/-0.1 p cavity pitch 8.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 5.5 0.1 d perforation diameter 1.55 0.10 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.4 0.1 b0 cavity width 5.2 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 9.3 0.1 ssop 20s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 9.0 0.1 k0 cavity depth 2.3 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 241 october 24, 2011 ssop 24s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.0 0.1 e perforation position 1.75 0.10 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 9.5 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.0 0.3 p cavity pitch 8.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 7.5 0.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 6.5 0.1 b0 cavity width 10.3 0.1 k0 cavity depth 2.1 0.1 t carrier tape thickness 0.30 0.05 c cover tape width 13.3 0.1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 242 october 24, 2011 carrier tape dimensions ssop 48w symbol description dimensions in mm w carrier tape width 32.00.3 p cavity pitch 16.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 14.20.1 d perforation diameter 2 min. d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 12.00.1 b0 cavity width 16.20.1 k1 cavity depth 2.40.1 k2 cavity depth 3.20.1 t carrier tape thickness 0.350.05 c cover tape width 25.50.1 ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 243 october 24, 2011 ! " # $ ! " # $ ht68f20/ht68f30/ht68f40/ht68f50/ht68f60 ht68fu30/ht68fu40/ht68fu50/ht68fu60 rev. 1.60 244 october 24, 2011 copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com |
Price & Availability of HT66F201109
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